JEDEC JESD12-4-1987 Method of Specification of Performance Parameters for CMOS Semicustom Integrated Circuits《CMOS Semicustom集成电路性能参数的规范方法》.pdf

1、Y e e - EIA JESDL2-4 87 m 323VbOO OOL(853 7 m I APRIL 1987 JEDEC STANDARD NO. 12-4 METHOD OF SPECIFICATION OF PERFORMANCE PARAMETERS , FR . ITS JEDEC Solid State Products Engineering Council EIA JESDL2-4 87 3234600 0004 854 N O T 1.C E This JEDEC Standard or Publication contains material that has be

2、en prepared, progressively reviewed, and approved through the JEDEC Council level and subsequently reviewed and approved by the EIA General Counsel. JEDEC Standards and Publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers,

3、facilitating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for his particular need. Exjstence of such standards shall not in any respect preclude any member or nonmember of JEDEC from manufacturing or sell

4、ing products not conforming to such standards, nor shall the existence of such standards preclude their voluntary use by those other than EIA members whether the standard is to be used either domestically or internationally. Recommended Standards are adopted by JEDEC without regard to whether or not

5、 their adoption may involve patents or articles, materials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC Standards or Publicat ions. The information included in JEDEC Standards and Publi

6、cations represents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC Standard or Publication may be further processed and ultimately become an EIA Standard. Inq

7、uiries, comments, and suggestions relative to the content of this JEDEC Standard or Publication should be addressed to the JEDEC Executive Secretary at EIA Headquarters, 2001 Eye Street, N.W., Washington, D.C. 20006. Published by ELECTRONIC INDUCTRIES ASSOCIATION Engineering Department 2001 Eye Stre

8、et, N.W. Washington, D.C. 20006 PRICE: $8.00 Printed in U.S.A. - EIA JESDL2-4 87 m 3234600 0004855 O m e JEDEC STANDARD NO. 12-4 METHOD OF SPECIFICATION OF PERFORMANCE PARAMETERS FOR CMOS SEMICUSTOM INTEGRATED CIRCUITS TABLE OF COEPEBPS Paragraph 1.0 METHOD OF SPECIFICATION OF PROPAGATION DELAY FOR

9、SEMICUSTOM ICs Page I 2.0 INTERCONNECT DELAY 11 3.0 PROPAGATION DELAY 4. o OVERSTRESS CAPABILITY I 5. O SPECIFICATION FOR INPUT AND OUTPUT PARAMETERS I (I/O BUFFERS) I 6.0 SPECIFICATION FOR APPROXIMATION OF POWER DISSIPATION PER CIRCUIT (BOTH STATIC AND DYNAMIC) 70 TYPICAL PERFORMANCE PARAMETERS e 1

10、1 12 12 13 15 4 FIGURE I Waveforms for Delays of Input Buffers 5 FIGURE 2 Waveforms for Delays of Internal Circuits FIGURE 3 Waveforms for Delays of Output Buffers 6 7 FIGURE 4 Waveforms for Delays of Three-State Internal Circuits FIGURE 5 Waveforms for Delays of Three-State Output Buffers 8 e 9 FIG

11、URE 6 Waveforms for Delays of Open-Drain Output Buffers EIA JESD12-4 ? m 3234600 0004856 2 m JEDEC STANDARD NO. 12-4 Page 1 METHOD OF SPECIFICATION OF PERFORMANCE PARAMETERS FOR CMOS SEMICUSTOM INTEGRATED CIRCUITS (From JEDEC Council Ballots JCB-83-30, 83-3011, and 86-29 formulated under the cogniza

12、nce of JC-44 Committee on Semicustom Integrated Circuits. ) 1.0 METHOD OF SPECIFICATION OF PROPAGATION DELAY FOR SEMICUSTOM ICs These specifications allow the circuit delays to be calculated as the sum of the cell or macro delays without needing parameters to account for the effect of interface dela

13、ys from input buffer to internal cell and from internal cell to output buffer. Load, temperature, and supply-voltage conditions must be included in the cell or macro delay specifications. Parameters to predict performance at other temperatures and power-supply voltages shall be included. Interconnec

14、t and load-dependent delays are specified separately. In stating performance specifications, manufacturing variation of process parameters must be accounted for. lei Types of Cells or Macros One or more propagation-delay specifications are defined for each generic type of cell or macro possible on a

15、ny semicustom circuit. Delay paths may have cells and macros that include any or all of the following generic types: 1.1.1 Input Buffers Cells or macros that accept inputs from sources external to the IC and produce outputs to cells or macros internal to the IC. 1.1.2 Internal Circuits Cells or macr

16、os that communicate only with other cells or macros on the same cell-based IC. 1.1.3 Output Buffers Cells or macros that accept inputs from cells or macros internal to the IC and propagate signals external to the IC. 1.1.4 Three-State Circuits (Internal and Output) Cells or macros whose outputs can

17、be placed in a high-impedance state and can also supply low- impedance high and low logic levels. EIA JESDL2-4 87 m 3234600 0004857 4 m JEDEC STANDARD NO. 12-4 Page 2 1.1.5 Open Drain Output Buffers Output buffers that have one low-impedance output logic level and a high-impedance output state 1.2 P

18、ropagation Delays of Cells or Macros The propagation delays and the enable and disable times for the various cells or macros shall be specified according to the following definition: Times are measured between the specified reference points on the input and output voltage waveforms with the specifie

19、d output changing from the defined high or low level or high-impedance state to another of these defined levels or states. The following propagation delay parameters must be specified. INTERNAL X X X X OUTPUT xi X X X THREE- STATE N-CHANNEL OPEN-DRAIN OUTPUT P-CHANNEL OPEN-DRAIN OUTPUT X X X X X X X

20、 X X X X X X X AtpLH, AtpHL, AtpzL, and AtpzH are factors that specify the impact that load capacitance has on propagation delay. Units for these parameters are ns/pF, and they are to be specified at room temperature . X X EIA JESDL2-4 87 m 3234b00 0004858 b m JEDEC STANDARD NO. 12-4 Page 3 1.2 Prop

21、agation Delays of Cells or Macros (continued) Internai cell or macro delays (tpLH, tpHL, tpZL, tpZH, tpLZ and tpHZ) are specified at O pf load. For three- state and open drain circuits, a resistance is specified from output to ground for tpHZ and output to VCC for tpLZ characterization. The resistan

22、ce is a function of the circuit drive capability. Input levels for characterization (vendor must specify VI: L ( T ) max VI H ( T ) min CMOS compatible inputs ov vcc TTL compatible inputs LVTTL compatible inputs I Internal circuits ov ov ov 3.0 v* 2.45 V* vc c * Consistent with JEDEC Standard No. 7A

23、, HCTXXX parts * Compatible with JEDEC Standard No. 8A for LVTTL interface levels EIA JESDL2-4 87 = 3234600 0004859 8 JEDEC STANDARD NO. 12-4 Page 4 1.2.1 Waveforms for Delays of Input Buffers (see 1.2.7) FIGURE 1 EIA JESD12-4 7 I 3234600 0004860 4 I JEDEC STANDARD NO. 12-4 Page 5 1.2.2 Waveforms or

24、 Delays of Internal Circuits (see 1.2.7) Vint(H) - INPUT ,+=i- - - - -Vint(ref) Vint(i) I I 4 PLH ty PHLA LA - -Vint(H) -Vint(ref) IN-PHASE I I I 7- OUTPUT FIGURE 2 I EIA JESDl2-4 7 m 3234b00 00048bl b m JEDEC STANDARD NO. 12-4 Page 6 1,2.3 Waveforms for Delays of Output Buffers (see 1.2.7) FIGURE 3

25、 EIA JESDL2-4 87 6 3234600 0004862 8 6 JEDEC STANDARD NO. .12-4 Page 7 I .2.4 Waveforms for Delays of Three-State Internal Circuits (see 1.2.7) - vin t(H) -.- - -Vint(ref) ., INPUT Vint(L) I I OUTPUT - OUTPUT OUTPUT - - W- - I I I - - - OUTPUT - OUTPUT -H - - ENABLED DISABLED ENABLED DISABLED ENABLE

26、D FIGURE 4 NOTE: The voltage waveform following a transition from low impedance tu high impedance is a strong function of the loading conneoted to the circuit of interest. EIA JESDL2-4 7 m 3234600 0004b3 T JEDEC STANDARD NO. 12-4 Page 8 1.2.5 Waveforms for Delays of Three-State Output Buffers (see 1

27、.2.7) - in t( H) -Vint(ref) Viiit(L) -u- - INPUT I I OUT-OF-PH ASE - OUTPUT I OUTPUT - - e - OUTPUT ENABLED I I - - - OUTPUT - -CC OUTPUT - - - EN ABLE D DISABLED ENABLED . DISABLED FIGURE 5 NOTE: The voltage waveform following a transition from low impedance to high impedance is a strong function o

28、f the loading oonnected to the ciccuit of interest. I EIA JESDL2-4 7 m 3234600 0004864 L I JEDEC STANDARD NO. 12-4 Page 9 OUTPUT FIGURE 6 NOTE: The voltage waveform following a transition from low impedance to high impedance is a strong function of the loading connected to the circuit of interest. .

29、 EIA JESDLZ-4 7 W 3234b00 0004b5 3 W JEDEC STANDARD NO. 12-4 Page IO 1.2.7 Definitions of Voltage Levels VIH (T)min. The minimum ac test value of high- level input voltage specified for input buffers. VIL ( T pax The maximum ac test value of low- level input voltage specified for input buffers. V(re

30、f) The reference points on the input waveform for input buffers. These are normally at the midpoint between VIL(T)max and VIH(T)min. Vint( H ) The minimum value of the high- level output voltage of input buffers, and internal and three- state internal circuits. This voltage is normally equal to Vcc

31、for CMOS circuits, Vint( L ) The maximum value of the low-level output voltage of input buffers, and internal and three-state internal circuits. This voltag is normally equal to zero volts for CMOS circuits. Vint(ref) The reference points on the output waveform for input buffers; the input and outpu

32、t waveforms for internal circuits; the input waveform for output buffers; and the input, output-disable, and output waveforms for three-state internal oircuits. These are .normally at the midpoint between Vint(H) and Vint(L) VOH ( T ) min The minimum ac test value of high- level output voltage speci

33、fied for output buffers. The maximum ac test value of low- level output voltage specified for output buffers. VOL ( T ) max - EIA JESDL2-4 7 3234600 00048bb 5 JEDEC STANDARD NO. 12-4 Page 11 1.2.7 Definitions of Voltage Levels (continued) V(ref) The reference points on the output waveform for output

34、 buffers. These are normally at the midpoint between VoH(T)min and VOL(T)max. An offset voltage to be specified by the vendor. NOTE: In JEDEC Std. 7A, Vx is specified as 10% of the power-supply voltage. VX 2.0 INTERCONNECT DELAY The. vendor shall specify the minimum and maximum delay effects of each

35、 interconnect medium (e.g., first-layer metal, second-layer metal, poly interconnect, diffused crossunder, wire bonds, package pins, etc.) used in a semicustom IC in accordance with the following: METAL (Each level)-pF/unit length and ohms/unit length of interconnect POLYSILICON (Each level)-pF/unit

36、 leng-bh and ohms/unit length of interconnect CONDUCTOR CROSSINGS (All applicable combinations)- pF/ crossing 1 e 3-0 PROPAGATION DELAY 3.1 Propagation Delay as a Function of Input Loading and Fan-Out Vendor shall specify the effective input capacitance for each cell or macro. This is used in conjun

37、ction with the interconnect capacitance to compute the load for a given gate. Propagation delay impact is then computed by multiplying the total load capacitance times the delta propagation delay (ns/pF) for that cell or macro. EIA JESDL2-4 87 M 3234600 O004867 7 JEDEC STANDARD NO 12-4 Page 12 3.2 P

38、ropagation Delay as a Function of sVariation of Junction Temperature and Supply Voltage The vendor shall specify the delay effects of changes in junction temperature and supply voltage on all cells or macros. Each change and its effect on delay are normally specified separately. Delays shall be stat

39、ed in terms consistent with other published data. For example, 4.0 OVERS.TRESS CAPABILITY 4.1 .-Sensi-biv.ity to Electrostatic Discharge The vendor shall describe the preferred test and limits r sensitivity to electrostatic discharge. For example, L-STD-883C Test Method 3015 specifies a test for mea

40、suring damage due to electrostatic discharge and may be referenced. 4.2 LatchiUp Specification The vendor should describe the constraints for preventing latch-up during operation, e.g., power-supply sequence. In addition, the vendor should describe the preferred test to determine latch-up sensitivit

41、y. NOTE TO READER: MIL-STD-883C DOES NOT SPECIFY A METHOD FOR ELECTRICALLY INDUCED LATCH-UP TESTING. JEDEC JC-40.2 IS DEVELOPING A STANDARD FOR LATCH-UP TESTING. ONCE ADOPTED, THIS STANDARD SHOULD BE REFERENCED FOR SEMICUSTOM IC TESTING. 5. O SPECIFICATION FOR INPUT AND OUTPUT PARAMETERS (I/O BUFFER

42、S) 5.1 Input Capacitance Input capacitance shall be measured with the input to be measured biased at a specified voltage with a specified signal amplitude of specified frequency applied. ._ EIA JESDL2-4 7 3234600 OOOYb 9 JEDEC STANDARD NO. 12-4 Page 13 5.2 Output Capacitance Output capacitance shall

43、 be measured with the output to be measured biased at a specified voltage with a specified signal amplitude of specified frequency applied. Any required combination and sequence of inputs to bring the output to the desired state must also be specified. 5.3 DC Parameters and 1/0 Macro Delay vs. Loadi

44、ng The vendor shall specify a complete list of input and output parameters for each input and output buffer offered. 5.3 DC Parameters and I/O Macro Relay VS. Loading (continued) These specifications shall include the following as a minimum: (a) Absolute maximum voltage limits at inputs and outputs

45、Absolute maximum current limits at inputs and outputs (b) (c.) Input impedance or input current limits t I (dl Current sinking and sourcing capability of outputs (e) Delay parameters of input and output buffers, (these data may be represented in graphical or tabular form) for various loading conditi

46、ons. 6, O SPECIFICATION FOR APPROXIMATION OF POWER DISSIPATION PER - CIRCUIT (BOTH STATIC AND DYNAMIC) The power dissipation of CMOS semicustom devices can be separa%ed into three components: (I) Quiescent power dissipation, PQ; (2) Intracell transient power dissipation? PT; and (3) Intercell transi

47、ent power dissipation, PN. The total power consumption can be determined a% any operating frequency as the- sum of these three components: Ptotal = PQ + PT + pN JEDEC STANDARD NO. 12-4 Page 14 6.1 Quiescent Power Dissipation m c=l Q = vCC -X 1 ICC(c) where: Vcc = power supply voltage. ICC() = quiesc

48、ent current of cell or macro c (usually increases with increasing temperature) NOTE: All inputs must be at either Vcc or ground during quiescent current measurement. 6.2 Intraoell Transient Power Dissipation m c=l 2 PT = VCC X 1 (fe X cc ) where: fc = input signal frequency for cell or macro c Cc =

49、equilvalent power dissipation capacitance for cell or macro c Cc must be specified for each cell or macro 6.3 Intercell Transient Power Dissipation (Including Output Buffer Power Dissipation) n=l where: fn = signal frequency for net n Cn = capacitance of net n (output load capacitance for output buffers) w = number of nets on circuit NOTE: Calculation of total circuit power dissipation is generally not done manually, because fc, fn and Cn are all design-dependent; and in addition Cn is routing dependent. Y EIA JESDL2-