JEDEC JESD15-2008 Thermal Modeling Overview.pdf

1、JEDEC STANDARD Thermal Modeling Overview JESD15 OCTOBER 2008 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors level and subsequently reviewed and approved by the JEDEC

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5、ally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may be further processed and ultimately become an ANSI standard. No claims to be in conformance with this standard may be made unless all requirements s

6、tated in the standard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC at the address below, or call (703) 907-7559 or www.jedec.org Published by JEDEC Solid State Technology Association 2008 3103 North 10th Stre

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9、 number of copies through entering into a license agreement. For information, contact: JEDEC Solid State Technology Association 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 or call (703) 907-7559 JEDEC Standard No. 15 -i- METHODOLOGY FOR THE THERMAL MODELING OF COMPONENT PACKAGES

10、Introduction In recent years, the role of thermal modeling in the thermal characterization of component packages has greatly increased in importance. Unlike thermal tests, in which the basic practices have achieved a certain level of maturity, thermal modeling methods and software are undergoing rap

11、id advancement. Hence this document and the associated series of documents are intended to promote the continued development of modeling methods, while providing a coherent framework for their use by defining a common vocabulary to discuss modeling, creating requirements for what information should

12、be included in a thermal modeling report, and specifying modeling procedures, where appropriate, and validation methods. This document provides an overview of the methodology necessary for performing meaningful thermal simulations for packages containing semiconductor devices. The actual methodology

13、 components are contained in separate detailed documents. JEDEC Standard No. 15 -ii- JEDEC Standard No. 15 Page 1 METHODOLOGY FOR THE THERMAL MODELING OF COMPONENT PACKAGES (From JEDEC Board Ballot JCB-08-27, formulated under the cognizance of the JC-15.1 Committee on Thermal Characterization.) 1 Sc

14、ope The modeling methodology described herein is distributed among several documents so that the appropriate combination of documents can be selected to meet specific thermal simulation requirements. This document provides the OVERVIEW. The rest of the documents are grouped as shown below: Figure 1

15、Diagram indicating modular structure of component modeling documents Because modeling methodologies and validation methods will change as technology changes, additional documents will be added to these groups as the needs arise and standards established. As appropriate, each of these documents will

16、contain terminology and symbolic definitions specific to the material covered by the individual document. JEDEC Standard No. 15 Page 2 2 Normative References 1. JESD51, Methodology for the Thermal Measurement of Component Packages (Single Semiconductor Device), Dec. 1995. 2. JESD51-12, Guidelines fo

17、r Reporting and Using Electronic Package Thermal Information, May 2005. 3 Rationale The junction temperature of a semiconductor device greatly influences the performance, reliability, and cost of the device. In recent years, thermal modeling has assumed increased importance in characterizing individ

18、ual components and predicting their junction temperature in both standard test and application environments. This document and the subsequent documents it calls on, provide a consistent framework for reporting thermal model results and the modeling and validation methods used. In particular cases do

19、cuments provide guidance in the use of particular modeling methods. The data can be used for package design evaluation, device (i.e., chip/package combination) characterization, reliability predictions, system-level thermal analyses, etc. 4 Purpose The output of a model is typically a junction tempe

20、rature. However, it is common to extract temperatures and fluxes from many locations in a model. If the situation being modeled consists of a component in a simulated JEDEC test environment, it is possible to extract thermal resistances and thermal characterization parameters1,2. 5 Results Presentat

21、ion The results of a model are not meaningful unless all the pertinent assumptions are provided along with them. The reporting requirements will depend upon the type of modeling methodology. The reporting requirements are presented in the documents in category Modeling Process. Furthermore, the accu

22、racy of a model should be demonstrated by using the appropriate Validation Process and Method. These documents will indicate the reporting requirements related to these procedures.Standard Improvement Form JEDEC JESD15 The purpose of this form is to provide the Technical Committees of JEDEC with inp

23、ut from the industry regarding usage of the subject standard. Individuals or companies are invited to submit comments to JEDEC. All comments will be collected and dispersed to the appropriate committee(s). If you can provide input, please complete this form and return to: JEDEC Attn: Publications De

24、partment 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 Fax: 703.907.7583 1. I recommend changes to the following: Requirement, clause number Test method number Clause number The referenced clause number has proven to be: Unclear Too Rigid In Error Other 2. Recommendations for correction: 3. Other suggestions for document improvement: Submitted by Name: Phone: Company: E-mail: Address: City/State/Zip: Date: