JEDEC JESD20-1990 Standard for Description of 54 74ACXXXXX and 54 74ACTXXXXX Advanced High-Speed CMOS Devices《54 74ACXXXXX和54 74ACTXXXXX高级高速CMOS设备的描述规范》.pdf

1、Reproduced By GLOBAL ENGINEERING DOCUMENTS With lhe Permission of EIA Under Royalty Aireetnent - JEDEC STANDARD STANDARD FOR DESCRIPTION OF 54/74ACxxxxX AND 54/74A= ADVANCED HIGH-SPEED CMOS DEVICES JEDEC STANDARD NO. 20 SEPTEMBER 1990 ELECTRONIC INDUSTRIES ASSOCIATION ENGINEERING MPARTMENT COPYRIGHT

2、 Electronic Industries AllianceLicensed by Information Handling ServicesI EIA JESDZO 70 W 3234b00 0503LOb ObT NOTICE JEDEC Standards and Publications contain material that has been prepared, progressively reviewed, and approved through the JEDEC Council level and subsequently reviewed and approved b

3、y the EIA General Counsel. JEDEC Standards and Publications are designed to sewe the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining with mi

4、nimum delay the proper product for his particular need. Existence of such standards shall not in any respect preclude any member or nonmember of JEDEC from manufacturing or selling products not confoming to such standards, nor shall the existence of such standards preclude their voluntary use by tho

5、se other than EIA members whether the standard is to be used either domestically or internationally, JEDEC Standards and Publications are adopted without regard to whether or not their adoption may involve patents or articles, materiais, or processes. By such action JEDEC does not assume any liabili

6、ty to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC Standards or Publications. The information included in JEDEC Standards and Publications represents a sound approach to product specification and application, principally from the solid state device manuf

7、acturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDECStandard or Publication may be further processed and ultimately become an EIA Standard. Inquiries, comments, and suggestions relative to the content of this DEC Publication should be addressed to the JEDEC Executive

8、 Secretary at EIA Headquarters, 2001 Pennsylvania Ave., N.W, Washington, D.C. 2ooo6 remporary Headquarters through March of 1990 - 1722 Eye St., N.W., Suite 30, Washington, D.C. 26). I I 1990 *ELECTRONIC INDUSTRIES ASSOCIATION Published by I ELECTRONIC INDUSTRIES ASSOCIATION Engineering Department 2

9、001 Pennsyhrania Ave., N.W. Washington, D.C. 2ooo6 Printed in U.S.A. All rights resewed COPYRIGHT Electronic Industries AllianceLicensed by Information Handling ServicesJEDEC Standard No. 20 STANDARD FOR DESCRIPTION OF 54/74ACXXXXX AND 54/74ACTXXXXX ADVANCED HIGH-SPEED CMOS DEVICES Section CONTENTS

10、Paqe SECTION 1 1. 54/74ACXXXXX STANDARD 1.1 Purpose and Scope 1.2 Purpose 1.3 Scope 1 1 1 1 2. DEFINITION 1 3. STANDARD SPECIFICATIONS 2 SECTION 2 1. 54/74ACTXXXXX STANDARD 1.1 Purpose and Scope 1.2 Purpose 1.3 Scope 4 4 4 4 2. DEFINITIONS 3. STANDARD SPECIFICATIONS 3.1 Absolute Maximum Continuous R

11、atings SECTION 3 Switching Waveforms for 54/74AC SECTION 4 Switching Waveforms for 54/74ACT SECTION 5 1. SCOPE 1.1 I, SECTION 6 1. SCOPE 4 4 5 7 13 19 19 20 COPYRIGHT Electronic Industries AllianceLicensed by Information Handling Services- EIA JESD20 90 W 3234bOO 0503108-q32 JEDEC Standard No. 20 ST

12、ANDARD FOR DESCRIPTION OF 54/74ACXXXXX AND 54/74ACTXXXXX ADVANCED HIGH-SPEED CMOS DEVICES CONTENTS Section SECTION 7 1. SCOPE 2. FORM OF DEVICE TYPE TABLES 3. INDEX OF DEVICE TYPE TABLES SECTION 8 1. 1.1 1.2 1.3 1.4 1.5 C, TEST PHILOSOPHY USE OF C, TO CALCULATE POWER DISSIPATION GENERAL MEASUREMENT

13、PROCEDURE MEASUREMENT PROCEDURE FOR DEVICES WITH COMMON CLOCK CIRCUITY OUTPUT LOAD CONSIDERATIONS SYMBOL DESCRIPTIONS SECTION 9 APPLICABLE JEDEC STANDARDS AND PUBLICATIONS Paqe 22 22 22 108 108 110 111 111 111 119 COPYRIGHT Electronic Industries AllianceLicensed by Information Handling Services - _

14、_ EIA JESD20 90 = 3234600 0503307 877 JEDEC Standard No. 20 Page 1 STANDARD FOR DESCRIPTION OF 54/74ACXXXXX AND 54/74ACTXXXXX ADVANCED HIGH-SPEED CMOS DEVICES (From JEDEC Council Ballot JCB-89-37, formulated under the cognizance of JC-40.2 Committee on CMOS Logic Devices.) SECTION 1 1, 54/74ACKKKxx

15、STANDARD 1.1 Purpose and Scope 1.2 Purpose The purpose of this standard is to develop a standard of 1154/74ACXXXXXtt series specifications to provide for uniformity, multiplicity of sources, elimination of confusion, and ease of device specification and design by users. 1.3 scope I This standard cov

16、ers standard specifications for description of the I154/74ACXXXXXit series advanced high-speed CMOS devices. 2. DEFINITIONS Indicates that the devices are specified overthe temperature range from -55OC to 125OC. Indicates that the devices are specified over the temperature range from -4OOC to 85OC.

17、54/74ACxxKxn series Includes devices whose input logic levels are defined herein for V, and VIL. Input switching thresholds are nominally one half the supply voltage. For driving CMOS input logic levels, incident wave-line-driving is specified for 50 ohm (74ACXXXXX) and 75 ohm (54ACXXXXX) lines. LOW

18、 Voltage Operation In accordance with the latest revision of JEDEC Standard No. 8 “Standard for Reduced Operating Voltages and Interface Levels for Integrated Circuits“ (March 1984). COPYRIGHT Electronic Industries AllianceLicensed by Information Handling Servicesi JEDEC Standard No. 20 Page 2 3. ST

19、ANDARD SPECIFICATIONS All voltages listed are referenced to ground except where noted. 3,1 Absolute Maximum Continuous Ratings (Notes 1 and 2): Supply Voltage, Va . -0.5 V to 6V C Input Dbde Current, IIK (VI O) -20 mA (v1.0) . 2omA or 6c Input Voltage, VI . .4.5 Vto VCC + 0.5 V (vo O) . ,so mA or Dc

20、output Vottage, VO 4.5 V to VCC + 0.5 V Dc Output Source or Sink Current per output pin, IO SO mA c vcc or Gwnd CUnent, kc Of IGND (forup to 4OUtpUtS per device, Not0 3) Ii mA Storage Temperature, Tio -5C to 150C NOTEI: AbrduuMuimumConnqsrnttosevrkmkyondwhiehdniig,toiIwbHormyocau. Funclionrlqmtimtm

21、HIGH to t Figure 3-6 54/74AC Three-State Waveforms COPYRIGHT Electronic Industries AllianceLicensed by Information Handling ServicesEIA JESD20 90 m 3234600 0503323 376 m Pulse Generator JEDEC Standard No. 20 Page 13 11842 11844 11841 1184 11853 11854 11861 11862 11863 11864 11873 11874 11881 11882 S

22、pecial IC- 520 1152 O = Non-ctandard characteristics amlv - a., d refer to section 9. COPYRIGHT Electronic Industries AllianceLicensed by Information Handling ServicesI - -I EIA JESD20 90 W 3234600 0503128 720 W JEDEC Standard No. 20 Page 20 SECTION 6 NON-STANDARD DEVICE SPECIFICATIONS 1 SCOPE The s

23、cope of this section shall be to establish measurement techniques and individual device specifications that are either not covered by the main standard or are special exceptions to this standard. The exceptions may be due to device functional, design, or application considerations. COPYRIGHT Electro

24、nic Industries AllianceLicensed by Information Handling Services EIA JESD20 90 3234b00 0503329 bb7 W JEDEC Standard No. 20 Page 21 AC/ACT SCHMITT TRIGGER INPUT SPECIFICATIONS Table 6-1 AC 110131 141 110141 11132 SYMBOL PARAMETER vcc 25.C 74ACXXXXX 54ACXXXXX V k UNIT VT+ Posit ive 3.0 2.2 2.2 242 Goi

25、ng 4.5 3.2 3.2 3.2 V Threshold 5.5 3.9 3.9 349 Voltage VT- Negative 3.0 .5 .5 . .5 Going 4.5 .9 .9 .9 V Threshold 5.5 1.1 1.1 1.1 Voltage Hysteresis 3.0 .3 1.2 .3 1.2 .3 1.2 Voltage 4.5 .4 1.4 .4 1.4 .4 1.4 V VH 5.5 -5 1.6 .S 1.6 -5 1.6 Table 6-2 ACT 11013, 14, 11014, 11132 SYMB PARAMETER 54ACTXXXXX

26、 “I VCC TA - 25C 74AtXXXhtX V UNIT Positive 4.5 Going 2.0 2.0 2.0 Voltage V VT+ Thr8ShOld Negative 4.5 Going .a .a .0 V VT- Threshold Voltaga Hysteresis 4.5 Voltaga .4 1.2 04 1.2 .4 1.2 V VH COPYRIGHT Electronic Industries AllianceLicensed by Information Handling Services- - - EIA JESD20 90 3239b00

27、0503330 387 = JEDEC Standard No. 20 Page 22 SECTION 7 SWITCHING SPEED STANDARDS FOR AC/ACT xXXXX DEVICES 1. SCOPE This section shall establish standard limits for switching parameters for the device types listed herein. For test methodology, refer to the waveforms and load circuits of Section 3. Ref

28、er to individual manufacturers data sheets for applicable propagation delay minimums. Derating calculations are not required, as the quoted parameter is valid 2. FORM OF DEVICE TYPE TABLES over the temperature range stated. Standardized limits .for switching parameters (dynamic characteristics) are

29、specified by part identifier in numerical order. See Paragraph 3. for index of device functions. All limits are in nanoseconds (ns), except fmax, which is in megahertz (MHz) . For each “Vcc = 5 f 0.5 V“ entry, two limits are shown separated by a I/ (e.g. limit a/lUt b). Limit a is for AC parts and l

30、imit b is for ACT parts. A dash -I is inserted whenever a number is not yet specified for a given device. The limits in the “VCC = 3.3 f 0.3 V“ row apply only to AC parts. 3. INDEX OF DEVICE TYPE TABLES Table 7.1 Gates and Simple Buffers/Inverters. 7.1.1 One Wide Buffers/Inverters: 04, 11004, 14, 11

31、014, 11034 7.1.2 Two Wide Gates: 00, 11000, 02, 11002, 08, 11008, 32, 11032, 86, 11086, 11132, 11810 7.1.3 Three Wide Gates: 10, 11010, 11, 11011, 11027 7.1.4 Four or More Wide Gates: 11013, 11020, 11021, 11030 Table 7.2 Bus Drivers, Buffers and Transceivers: 240, 11240, 241, 11241, 244, 11244, 245,

32、 11245, 367, 368, 540, 541, 11640 Table 7.3 Flip Flops and Registers: 74, 11074, 109, 11109, 112, 11112, 174, 175, 11175, 273, 374, 11374, 11379, 11534, 574, 646, 648 Table 7.4 Latches: Table 7.5 Encoders and Decoders: 373, 11373, 11533, 563, 573 138, 11138, 139, 11139, 11238, 11239 COPYRIGHT Electr

33、onic Industries AllianceLicensed by Information Handling ServicesEIA JESD20 90 W 3234600 0503131 215 W r I JEDEC Standard No. 20 Page 23 SECTION 7 SWITCEING SPEED STANDARDS FOR AC/ACT XXXXX DEVICES 3. INDEX OF DEVICE TYPE TABLES (CONTINUED) Table 7.6 Digital Multiplexexs and Data Selectors: 151, 111

34、51, 153, 157, 158, 11158, 251, 11251, 253, 11253, 257, 11257, 258, 11258, 11353 Table 7.7 Analog Switches, Multiplexers/Demultiplexers: see Section 6 Table 7.8 Asynchronous Counters: Table 7.9 Synchronous Counters: 11160, 161, 11162, 163, 11190, 191, 11191 Table 7.10 Shift Registers: 164, 166, 11194

35、, 11898 Table 7.11 Multivibrators and One Shots: Table 7.12 Comparators: 11520, 11521 Table 7.13 Parity Checkers, Generators and Encoders: 280, 11280, 11286 Table 7.14 Register Files, Logic Memories, Memory Management and Support Functions: 67 O Table 7.15 FIFOs: Table 7.16 ALUS, Adders, Multipliers

36、 and Other Arithmetic Functions: Table 7.17 Phase Locked Loops: see Section 6 COPYRIGHT Electronic Industries AllianceLicensed by Information Handling Services15.0 17.3 19.0 74AC/ACTXXXXX 15.2 11. o/- 54AC/ACTXXXXX Unit 16.8 ns ns 12. o/- MaxiInlRn propagation delay V 3.3 f 0.3 Sf 0.5 JEDEC Standard

37、 No. 20 Page 24 TABLE 7.1 GATES AND SIMPLE BUFFERS/INVRTERS 7.1.1 One Wide Buffers/Inverters AC/ACTO 4 f I vcc TA - 25 C 74AC/ACTXXXXX 54AC/ACTXXXXX I Unit Iymboi I Parameter V 3.3 f 0.3 I I I I Maximum propagation delay ns 5f 0.5 7.W7.9 7.7/9.0 I 8.5/9.3 ns 1 I AC/ACT11004 4AC /ACTxXXXX 5 4AC /ACTx

38、XXXX - Unit TA = 25 C vcc V Parameter Maximum propagation delay 3.3 f 0.3 10.0 I 10.4 9.0 ns - ns 5f 0.5 6.3/9. O 7.1/9.7 7.5/10.3 AC/ACT14 vcc Paramet er TA = 25O C LPHLt :PLH 14.0 10. o/- I I I COPYRIGHT Electronic Industries AllianceLicensed by Information Handling ServicesEIA JESDZO so m 334boo

39、0503133 ow m 7 JEDEC Standard No. 20 Page 25 TABLE 7.1 GATES AND SIMPLE BUFFERS/INVERTERS (CONTINUED) 7.1.1 One Wide Buffere/Inverters (continued) AC/ACT11014 vcc Par ame t e r TA = 25 C V 4AC/ACTXXXXX 54AC/ACTXXXXX Unit PHI, Maximum 3.3 f PLH propagation delay I 0.3 I I 9.3 ne 6 o 9/- 7.4/- 7 * 7/-

40、 ns AC/ACT11034 vcc TA = 25 C 74AC/ACTXXXXX V Parameter 5 4AC / ACTXXXXX Unit ne ne 3*3 0.3 *I 9.1 I 10.1 Maximum propagation delay 10.7 6.9/9.9 I 6.3/8.9 7.4/10.5 I 7.1.2 Two Wide Gates AC/ACTO O vcc V Parameter TA = 25 C 11.2 Unit lQAC/ACTXXXXX %AC /ACTxxxxX Maximum propagation delay 3.3 f 0.3 12.

41、9 14.2 ns - 5f 0.5 8.5/12 .O 8 .O/ll .O 8.8/13.2 ns COPYRIGHT Electronic Industries AllianceLicensed by Information Handling ServicesEIA JESD20 90 W 3234600 0503334 T24 W JEDEC Standard No. 20 Page 26 TABLE 7.1 GATES AND SIMPLE BUEFERS/INVERTERS (CONTINUED) 7.1.2 Two Wide Gates (continued) AC/ACT110

42、00 vcc Paramet er TA = 25 C 74AC/ACTXXXXX 54AC/ACTXXXXX Unit V Maximum 3.3 f propagation delay 0.3 9.8 11.1 11.9 ns 5f 0.5 6.5/10.9 7.4/12.3 a. 1113.3 ns AC / ACT O 2 vcc Symbol Parameter TA = 25 C 74AC/ACTXXXXX 54AC/ACTXXXXX Unit V tpHL, Maximum 3.3 f tpLH propagation delay 0.3 13.5 14.6 16.1 ns 5f 0.5 9.6/10.2 10.4/11.1 11.5/12.2 ns AC/ACT11002 vcc Symbol Parameter TA = 25“ C 74AC/ACTXXXXX 54AC/ACTXXXXX Unit V tpHL, Maximum 3.3 f tpLH propagation delay 0.3 8.6 9.9 10.7 ns 5f 0.5 6.U9.4 6.9/10.6 7.4m.3 ns COPYRIGHT Electronic Industries AllianceLicensed by Information Handling Services