JEDEC JESD214-2015 Constant-Temperature Aging Method to Characterize Copper Interconnect Metallization for Stress-Induced Voiding.pdf

1、JEDEC STANDARD Constant-Temperature Aging Method to Characterize Copper Interconnect Metallization for Stress-Induced Voiding JESD214 FEBRUARY 2015 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through

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9、State Technology Association 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 or refer to www.jedec.org under Standards-Documents/Copyright Information. JEDEC Standard No. 214 -i- CONSTANT-TEMPERATURE AGING METHOD TO CHARACTERIZE COPPER INTERCONNECT METALLIZATIONS FOR STRESS-INDUCED V

10、OIDING CONTENTS Page1 Scope 12 Stress induced voiding in copper 12.1 Stress-induced voids 12.2 Stress temperature 22.3 Geometry linewidth dependence of SIV risk 32.4 Via size dependence of SIV risk 2.5 SIV under multiple vias 562.6 Metal thickness dependence of SIV risk 82.7 SM lifetime model 93 Con

11、stant temperature aging test method 103.1 Test structures 103.2 Test temperatures 3.3 Test conditions, sample size and measurements 15153.4 Failure criteria 153.5 Passing criteria 164 Data to be reported 175 References 18JEDEC Standard No. 214 Page 1 CONSTANT-TEMPERATURE AGING METHOD TO CHARACTERIZE

12、 COPPER INTERCONNECT METALLIZATIONS FOR STRESS-INDUCED VOIDING (From JEDEC Board Ballot JCB-15-06, formulated under the cognizance of the JC-14.2 Committee on Wafer-Level Reliability.) 1 Scope This document describes a constant temperature (isothermal) aging method for testing copper (Cu) metallizat

13、ion test structures on microelectronics wafers for susceptibility to stress-induced voiding (SIV). This method is to be conducted primarily at the wafer level of production during technology development, and the results are to be used for lifetime prediction and failure analysis. Under some conditio

14、ns, the method may be applied to package-level testing. This method is not intended to check production lots for shipment, because of the long test time. Dual damascene Cu metallization systems usually have liners, such as tantalum (Ta) or tantalum nitride (TaN) on the bottom and sides of trenches e

15、tched into dielectric layers. Hence, for structures in which a single via contacts a wide line below it, a void under the via can cause an open circuit at almost the same time as any percentage resistance shift that would satisfy a failure criterion. The method assumes that void growth (and therefor

16、e resistance changes) can be modeled as described by Ogawa, et al.1, Yao, et all 2, 3 Fischer et al. 5,6, to obtain a median lifetime, an effective activation energy, and an acceleration factor for lifetime. 2 Stress induced voiding in copper 2.1 Stress-induced voids Stress migration (SM) or stress-

17、induced-voiding (SIV) is one of the key aspects of Cu interconnect technology reliability qualification. The SIV damages are caused by the stress gradient as driving force through the means of diffusion. For Cu interconnects, it is known qualitatively that the intrinsic SIV risk is higher for a wide

18、 line relatively to a narrow line structure with a fixed single via size 1-4, 7-11. As industrial standards, SM reliability data have been treated qualitatively to define pass or fail criteria. The agreed guard-band of “zero fails during a fixed time period” as SM qualification passing criteria has

19、been generally accepted by the industry 8. This approach was inherited from Al SIV testing method for Cu SIV guard-band but with certain degrees of uncertainty. With the further technology scaling, the Cu SIV reliability margin becomes narrower. Therefore, the old traditional standard could lead to

20、even larger error bars for reliability projections. In order to overcome this known trend of increasing SIV risk, a quantitative SIV lifetime estimation method is needed. JEDEC Standard No. 214 Page 2 2.1 Stress-induced voids (contd) In recent years, the SIV mechanism has been investigated to reduce

21、 SIV risk and established SM qualification methodology 1-4, 7. Due to the improvement of integration process, progress has been made in SM reliability performance in meeting the design lifetime goals. In general, observation of SM fails is not expected for design rule compliant (DRC) linewidth struc

22、tures even at the worst temperatures during SM reliability testing period (i.e., 500 h to 1000 h). It is possible to measure SM fails from reasonable wide linewidth test structures within reasonable testing period of time. In 2,3, a geometry linewidth dependent factor was introduced to support an SM

23、 model for lifetime extrapolation. The quantified linewidth dependent SM data from 45 nm, 32 nm, and 28 nm show a common power-law factor M. This further supports the SM model with a geometry linewidth factor for acceleration 2,3. In this spec, in addition to the traditional method, we will apply th

24、e SM lifetime model and the equation to develop an SM reliability qualification methodology for meeting the product design lifetime. 2.2 Stress temperature Cu SM data show a strong temperature dependence of SM lifetime. Based on the Creep voiding rate model by McPherson 2) MTF increases as temperatu

25、re decreases below T0. MTF reaches its minimum at a “sweet spot” near 200 C to 225 C. The location of the “sweet spot” may vary depending on wafer process details; 3) below T0but above the “sweet spot”, the MTF distribution reverses its direction; 4) Close to the operating temperature range, i.e., 1

26、25 C to 100 C, the SM data are mostly Arrhenius-like and dominated by the diffusion term. The temperature dependence below the “sweet spot” (i.e., 175 C to 100 C) can be approximately treated by Arrhenius model. 2.3 Geometry linewidth dependence of SIV risk The linewidth dependence of SIV risk is an

27、 important feature for setting design rules and reliability qualification tests. As we have shown in section A that SM MTF values are linewidth dependent. In general, the SIV risk increases as linewidth increases for a single via. The MTF values follow a power-law as a function of linewidth as shown

28、 in Figure 2. The MTF power-law relation can be expressed as: MTF=CW-2.94(2) where W is the linewidth or plate size and C is a normalization constant. 2.94 is the power-law component value from the fit. JEDEC Standard No. 214 Page 4 2.3 Geometry linewidth dependence of SIV risk (contd Figure 2 shows

29、 the MTF power-law relation of linewidth measured from wafers of technologies of 45 nm, 32 nm, and 28 nm. It is noticeable that SM data from all three technologies follow the power-law by linewidth and the power components of the three set of data are nearly the same, 2.94. The power component value

30、 of 3 indicates the possible relation to a particular voiding nucleation mechanism 14,15. We believe that the MTF power-law relation of linewidth reflects the intrinsic nature of SM linewidth scaling. It can be expressed in general terms as: MTF=CW-M(3) where M is the geometry stress component. The

31、M values can be fitted and checked from SM testing results. Its value may be altered in accordance to the wafer process and presence of intrinsic failures. For this illustration, the M values extracted from three technologies are consistently close to 3. It is recommended that characterization is pe

32、rformed to understand the intrinsic SM property and establish validity and correlation to this prescribe model in order to determine applicability, especially in the smaller regions adjacent or outside line width of figure 2. Figure 2 Power-law relation of MTF vs linewidth From Figure 2, it is notic

33、eable since the DRC linewidth is 10%; 2) Resistance increase (R) for single via 100% These are failure criteria for general practice in SM reliability evaluations. Individual company can revise the resistance increase numbers in their special cases if needed. JEDEC Standard No. 214 Page 16 3.5 Passi

34、ng criteria a) Zero DRC test structure fails for all testing temperatures within 1000 h. The a) criteria is the traditional method of “zero fails during a fixed time period”, which will explore the SIV risk of DRC test structures as well as extrinsic defects during the 1000 h tests. This is a must-h

35、ave passing criterion. For the purpose of estimating the SM margin and the extrapolation of product SM lifetime, we introduce the 2ndcriterion for company to follow. The details of the execution of this b) criterion are based on companys choice on an accelerated method of SM lifetime model (see 2.7)

36、. b) Zero SM fails for selected wide line via chains within a fixed period, e.g., 250 h, 500 h, or shorter, depending on the choices of wide line widths of the test structures. For example, if there is zero 2 m via chain fail within 500 h at 175 C for 32 nm and 28 nm, the product SM lifetime will re

37、ach the 10 year goal. The detailed choices of selected line width value and no fail hour period can be determined by each company, based on the SM model described in 2.7. JEDEC Standard No. 214 Page 17 4 Data to be reported After completion of the test, the information listed in the following paragr

38、aphs should be reported. 4.1 Bake Temperatures (see 3.2) 4.2 Measurement Intervals List the cumulative time between the beginning of the test and each resistance readout (see 3.3). 4.3 Failure Criterion List the criteria used to define failure (e.g., percentage resistance shift, open circuit, etc.)

39、(see 3.4). 4.4 Sample Tested Describe the sample tested, including the number of wafers, the number of chips per wafer, the macro names and number of structures on each chip (see 3.3 and 3.1). 4.5 Stress Structure Describe the features of each test structure used, and illustrate with drawings if pra

40、ctical (refer to 3.1). 4.6 Initial Resistance Plot distribution plots of initial resistance of each test structure (see 3.3). 4.7 Stress Data Plot the distributions of fractional resistance change versus stress time for each structure and indicate the failure criteria on the plot (see 3.3 and 3.4).

41、4.8 SM Reliability ligetime Estimated SM margin and lifetime at use conditions: based on the failure conditions of wide line SM test structures, which are non-DRC. We can estimate the SM reliability lifetime by applying the SM lifetime model in 2.7. As an example, if there are no fails from 2 m widt

42、h via chains within 500 h at 175 C for 32 nm and 28 nm technology wafers, the SM lifetime will reach 10 year lifetime goal. JEDEC Standard No. 214 Page 18 5 References 1 E.T. Ogawa, et al., “Stress-Induced Voiding Under Vias Connected To Wide Cu Metal Leads”, International Reliability Physics Sympos

43、ium Proceedings, 2002, pp. 312-321. 2 H.W. Yao, et al., “Stress migration model for Cu Interconnect Reliability Analysis,” J. Appl. Phys., vol. 110, 2011, pp. 073504-073509. 3 H. W. Yao et al, “Stress-induced-voiding Risk Factor and Stress Migration Model for Cu Interconnect Reliability”, IEEE IRPS

44、Symposium Proceedings of 2013, pp.2C.5.1- 2C.5.8. 4 C. Zhai, et al., “Simulation and Experiments of Stress Migration for Cu/low-k BEoL”, IEEE TDMR, 2004, pp. 523-529. 5 A. H. Fischer, A. Zitzelsberger, The quantitiative assessment of stress-induced voiding in process qualification, in 2001 IEEE Inte

45、rnational Reliability Physics Symposium Proceedings (39th annual, Orlando, FL), IEEE, NJ, 2001, pp. 334-340. 6 A. H. Fischer, et al., New Approaches for the Assessment of Stress-Induced Voiding in Cu Interconnects, IEEE IITC, 2002. 7 Baozhen Li and Dinesh Badami, “Stress Voiding Characteristics of C

46、u/Low K Interconnects Under Long Term Stresses,” International Reliability Physics Symposium Proceedings, 2012, pp. 5E.2.1- 5E.2.6. 8 Joint Electron Device Engineering Council/Fabless Semiconductor Association joint publication, JEDEC, JP001.01. 9 K.Y.Y. Doony, et al., “Stress-induced voiding and it

47、s geometry dependency characterization,” International Reliability Physics Symposium Proceedings, 2003,pp. 156-160. 10 T. Suzuki, et al., “Stress migration phenomenon in narrow copper interconnects,” J. Appl. Phys., vol. 101, 2007, pp. 044513. 11 W.Shao, et al., “The effect of line width on stress-i

48、nduced voiding in Cu dual damascene interconnects,” Thin Solid Films 504, 2006, pp. 298. 12 Chang-Chun Lee, et al., “A New Stress Migration Failure Mode in Highly Scaled Cu/Low- k Interconnects”, IEEE TDMR, 2012, pp. 529-531. 13 S.F. Chen, et al., “Investigation of New Stress Migration Failure Mod e

49、s in Highly Scaled Cu/Low-k Interconnects,” Reliability Physics Symposium Proceedings, 2012, pp. 5E.3.1- 5E.3.5. 14 J.W. Cahn, “Transformation kinetics during continuous cooling“. Acta Metallurgica 4, 1956, pp. 572575. 15 K.N. Tu, J.W. Mayer and L.C. Feldman, Electronic Thin Film Science for Electronic Engineers and Material Scientists, New York, NY: Macmillan Publishing Company, 1992. 16 J.W. McPherson and C. F. Dunn, “A model for stress-induced metal notching and voiding in very large-scale-integrated Al-Si(1%)