JEDEC JESD216B-2014 Serial Flash Discoverable Parameters (SFDP).pdf

1、 JEDEC STANDARD Serial Flash Discoverable Parameters (SFDP) JESD216B (Revision of JESD216A, July 2013) MAY 2014 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors level

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9、rth 10th Street Suite 240 South Arlington, VA 22201-2107 or refer to www.jedec.org under Standards-Documents/Copyright Information. JEDEC Standard No. 216B -i- SERIAL FLASH DISCOVERABLE PARAMETERS (SFDP) STANDARD Contents Page Foreword ii Introduction ii 1 Scope 1 2 Normative references 1 3 Terms an

10、d definitions 1 4 Read SFDP Command Protocol 4.1 Instruction 4.2 Address 4.3 Wait States 4.4 Clock Rate 4.5 Command Modes 3 3 3 3 3 35 Read SFDP Behavior 5.1 Security 5.2 Reset and Hold Functions 5.3 Read Wraps 5.4 SFDP Address Boundary Wrap 5.5 Reserved SFDP Locations 5 5 5 5 6 6 6 SFDP Database 6.

11、1 SFDP Header Structure 6.2 SFDP Header 6.3 Parameter Headers 6.4 JEDEC Basic Flash Parameter Header and Tables 6.5 JEDEC Sector Map Parameter Table 6.6 JEDEC 4 Byte Address Instruction Table 6 6 7 8 12 30 39 7 Rules for Header and Table Additions and Modifications 42 8 Legacy Compatibility 42 Annex

12、 A (informative) Example SFDP Discovery Code Annex B (informative) Example SFDP Sector Map Discovery Code Annex C (informative) Procedure For Requesting Function Specific ID Annex D (informative) Differences between revisions 43 45 50 50Figures 1 Read SFDP (1-1-1) Mode Timing Diagram 2 Read SFDP (2-

13、2-2) Mode Timing Diagram 3 Read SFDP (4,4,4) Mode Timing Diagram 4 Overall Header Structure 5 Examples of a Basic SFDP Header and Basic with a Second Parameter Header 6 Examples of an SFDP Header with two basic parameter tables 7 Examples of an SFDP Header with two basic parameter tables and one opt

14、ional (4 Byte Addressing) Function Specific table 4 4 5 6 11 11 12JEDEC Standard No. 216B -ii- Foreword This standard was prepared by the JEDEC SFDP Task Group authorized by the JC-42.4 Committee Chairman. It was derived from prior work done by Intel on their Serial Flash Discoverable Parameters Gui

15、delines document. The intended audience is serial flash vendors and engineers writing device drivers for SFDP compliant serial flash devices. The participating SFDP TG members were volunteers from AMD, ASPEED, Emulex, HP, Intel, Macronix, Micron, Microchip, Sanyo, Spansion, and Winbond. Introduction

16、 The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional and feature capabilities of serial flash devices in a standard set of internal parameter tables. These parameter tables can be interrogated by host system software to enable adjustments

17、 needed to accommodate divergent features from multiple vendors. The SFDP standard defines a common parameter table describing important device characteristics and serial access methods used to read the parameter table data. Special Function parameter tables for erase sector address map and 4-byte a

18、ddress instructions are added in this revision of this standard. Additional parameter headers and tables can be specified by future revisions of this standard or by flash vendors and are optional. JEDEC Standard No. 216B Page 1 SERIAL FLASH DISCOVERABLE PARAMETERS (SFDP) STANDARD (From JEDEC Board B

19、allot JCB-14-08, formulated under the cognizance of the JC-42.4 Committee on Nonvolatile Memory.) 1 Scope The SFDP standard defines the structure of the SFDP database within the memory device and methods used to read its data. The JEDEC-defined header with Parameter ID FF00h and the related Basic Pa

20、rameter Table is mandatory. This header and table provide basic information for a Serial Peripheral Interface (SPI) protocol memory. Additional headers and tables are optional. The read command protocol using various I/O modes and standard clock rate are specified. The device electrical parameters a

21、re not specified. 2 Normative reference The following normative documents contain provisions that, through reference in this text, constitute provisions of this standard. For dated references, subsequent amendments to, or revisions of, any of these publications do not apply. However, parties to agre

22、ements based on this standard are encouraged to investigate the possibility of applying the most recent editions of the normative documents indicated below. For undated references, the latest edition of the normative document referred to applies. 1. JEP106, Standard Manufacturers Identification Code

23、 (contact jedec.org for the latest revision of this document) 2. NIST SP800-147, BIOS Protection Guidelines (http:/csrc.nist.gov/publications/nistpubs/) 3 Terms and definitions For the purposes of this standard, the following terms and definitions apply: 00b: The b suffix indicates the 00 digits are

24、 a binary representation of the number. 00h: The h suffix indicates the 00 digits are a hexadecimal representation of the number. 0x00: The 0x prefix indicates the 00 digits are a hexadecimal representation of the number. This form is used in the C sample code in Annexes. Address: The three or four

25、byte value following some instructions that is used to select a location within an address space of the flash memory. JEDEC Standard No. 216B Page 2 3 Terms and definitions (contd) Basic Parameter Table: The table pointed to by Parameter ID FF00h. Contains general information about the flash devices

26、 capabilities. Block: A group of contiguous sectors. Command: The combination of the instruction, address, optional mode bits, wait states, and data cycles used to initiate functions or transfer information between the controller and the serial flash. Controller: The serial bus master Double Transfe

27、r Rate (DTR): Instruction, address, and/or data may be input or output on both the rising and falling edges of the clock. Dummy Cycles: Clock cycles during which no data is transferred to or from a memory. DWORD: Four consecutive 8-bit bytes used as the basic 32-bit building block for headers and pa

28、rameter tables. Instruction: The one byte code used to initiate a function in the serial flash or identify the type of information transfer between the controller and the serial flash. Mode Bits: Optional control bits that follow the address bits. These bits are driven by the controller if they are

29、specified. Wait States: Required clock cycles between the address bits or optional mode bits and the start of data when reading from the flash device. Some device data sheets describe these as dummy cycles because no information is transferred between the controller and memory during these cycles. N

30、either controller nor memory are required to drive the data lines during these cycles. Read Latency: On flash read instructions, the total number of clocks between end of address and the start of data. The sum of clocks for mode bits and clocks for wait states equals the Read Latency. Sector: The mi

31、nimum granularity - size and alignment - of an area that can be erased in the data array of a flash memory device. Different areas within the address range of the data array may have a different minimum erase granularity (sector size). (x-y-z): Command mode nomenclature used to indicate the number o

32、f active pins used for the instruction (x), address (y), and data (z). At the present time, the only valid Read SFDP command modes are: (1-1-1), (2-2-2), and (4-4-4) JEDEC Standard No. 216B Page 3 4 Read SFDP Command Protocol 4.1 Instruction The Read SFDP instruction code is 5Ah. 4.2 Address Indicat

33、es the starting byte address in the SFDP area and is always expressed as a three byte field. 4.3 Wait States Following the address, eight clocks are required before valid data is clocked out. 4.4 Clock Rate SFDP compliant devices must support 50 MHz operation for the Read SFDP command (instruction 5

34、Ah). Devices may support a wider frequency range, but a controller can always run SFDP cycles at 50 MHz or less and get valid results. 4.5 Command Modes The Read SFDP command can be used with device supported modes of (1-1-1), (2-2-2), or (4-4-4), but the instruction (5Ah), address (24 bits), eight

35、wait states, and 50 MHz requirements remain the same. Support for SFDP does not imply or require that the flash device support 2-2-2 or 4-4-4 mode. If the controller knows a priori the mode in which the flash device is configured, then it can issue the Read SFDP command in that mode. If the controll

36、er does not know, then a suggested algorithm is to try to read the SFDP signature (see 6.1) in 4-4-4 mode, if that fails try 2-2-2 mode, and if that fails try 1-1-1 mode. Timing Diagram Signal Definitions: S# = Select, low active. Memory device selection signal also often referred to as Chip Select

37、or Chip Enable C = Clock. Serial clock to the memory also often referred to as SCLK. DQ0 = Data input or output zero. The least significant memory data input or output also often referred to as IO0 or Serial Input (SI) when not used for two or four bit data I/O. DQ1 = Data input or output one. The n

38、ext most significant memory data input or output above DQ0, also often referred to as IO1 or Serial Output (SO) when not used for two or four bit data I/O. DQ2 = Data input or output two. The next most significant memory data input or output above DQ1, also often referred to as IO2 or Write Protect,

39、 low active (WP#) when not used for four bit data I/O. DQ3 = Data input or output three. The most significant memory data input or output, also often referred to as IO3 or Hold, low active (HOLD#) when not used for four bit data I/O. JEDEC Standard No. 216B Page 4 4.5.1 Read SFDP (1-1-1) Mode CDQ0S#

40、DQ12321 3456789 303122 1 0High ImpedanceInstruction24-bitaddress001011 100765432 01Dummycycles(8)DOUT1DOUT239 40 41 42 43 44 45 46Figure 1 Read SFDP (1-1-1) Mode Timing Diagram 4.5.2 Read SFDP (2-2-2) Mode CDQ0S#DQ1 2321 3 4 5 14 1522 2 0Instruction 24-bitaddress01100110076543201Dummycycles(8)DOUT1D

41、OUT221203123 24 25 26Figure 2 Read SFDP (2-2-2) Mode Timing Diagram JEDEC Standard No. 216B Page 5 4.5.3 Read SFDP (4-4-4) Mode CDQ0S#DQ121367Instruction 24-bitaddress0100176543201Dummycycles(8)DOUT1DOUT2DQ2 1 0DQ3 0 1 23 19 7322 18 6221 17 5120 16 4015 16Figure 3 Read SFDP (4-4-4) Mode Timing Diagr

42、am 5 Read SFDP Behavior 5.1 Security The SFDP and flash memory address ranges must never overlap. This ensures that address range checking the controller may perform to prevent access to security keys or other sensitive information stored in flash cannot be bypassed. Also, for PC BIOS applications n

43、on-overlap is required to comply with NIST SP800-147. Addresses beyond the end of the SFDP tables must not alias into the flash memory. Regardless of the implementation, writes to SFDP tables must be permanently disabled before the memory device is released to a customer by the memory vendor factory

44、. 5.2 Reset and Hold Functions Reset and Hold functionality will be available during the Read SFDP command if the memory device command mode supports these features. 5.3 Read Wrap Not supported with the Read SFDP command-even when a memory device defaults to Read Wrap-around mode for other read comm

45、ands. Only continuous (sequential) read is supported with the Read SFDP command. JEDEC Standard No. 216B Page 6 5.4 SFDP Address Boundary Wrap Device behavior when the Read SFDP command crosses the SFDP structure boundary is not defined except for the security restriction specified in 5.1. There is

46、no requirement for the address counter to wrap back to the beginning of the structure and the data read after that point is not specified. 5.5 Reserved SFDP Locations The content of reserved SFDP locations (memory within the SFDP address space that has not yet been defined or used) is not specified,

47、 but recommended to be all FFh. 6 SFDP Database 6.1 SFDP Header Structure The format of the SFDP header is shown in Figure 4. 31:24 23:16 15:8 7:0 Hex byte location SFDP Header Serial Flash Discoverable Parameters (SFDP) Signature = 50444653h 3h:0h Byte 3 = “P“ Byte 2 = “D“ Byte 1 = “F“ Byte 0 = “S“

48、 Unused (set to FFh) Number of Parameter Headers (NPH) SFDP Major Revision SFDP Minor Revision 7h:4h 1stParameter Header Parameter Length (in double words) Parameter Major Revision Parameter Minor Revision Parameter ID LSB JEDEC ID (00h) Bh:8h Parameter ID MSB JEDEC ID (FFh) Parameter Table Pointer

49、(byte address) Fh:Ch 2ndParameter Header (optional) Parameter Length (in double words) Parameter Major Revision Parameter Minor Revision Parameter ID LSB 13h:10h Parameter ID MSB Parameter Table Pointer (byte address) 17h:14h . Nth Parameter Header (optional) Parameter Length (in double words) Parameter Major Revision Parameter Minor Revision Parameter ID LSB Parameter ID MSB Parameter Table Pointer (byte address) Figure 4 Overall Header Structure JEDEC Standard No. 216B Page 7 6.2 SFDP Header The SFDP