JEDEC JESD22-A110E-2015 Highly Accelerated Temperature and Humidity Stress Test (HAST).pdf

1、 JEDEC STANDARD Highly Accelerated Temperature and Humidity Stress Test (HAST) JESD22-A110E (Revision of JESD22-A110D, November 2010) JULY 2015 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the

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5、tions represents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may be further processed and ultimately become an ANSI standard. No c

6、laims to be in conformance with this standard may be made unless all requirements stated in the standard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC at the address below, or call (703) 907-7559 or www.jedec.

7、org Published by JEDEC Solid State Technology Association 2015 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 This document may be downloaded free of charge; however JEDEC retains the copyright on this material. By downloading this file the individual agrees not to charge for or res

8、ell the resulting material. PRICE: Please refer to www.jedec.org Printed in the U.S.A. All rights reserved PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by JEDEC and may not be reproduced without permission. Organizations may obtain permission to reproduce a limited number of copies thr

9、ough entering into a license agreement. For information, contact: JEDEC Solid State Technology Association 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 or call (703) 907-7559 JEDEC Standard No. 22-A110E Page 1 Test Method A110E (Revision of A110D) TEST METHOD A110E HIGHLY-ACCELERA

10、TED TEMPERATURE AND HUMIDITY STRESS TEST (HAST) (From JEDEC Board Ballot JCB-15-24, formulated under the cognizance of JC-14.1 Committee on Reliability Test Methods for Packaged Devices.) 1 Scope The Highly-Accelerated Temperature and Humidity Stress Test is performed for the purpose of evaluating t

11、he reliability of non-hermetic packaged solid-state devices in humid environments. It employs severe conditions of temperature, humidity, and bias which accelerate the penetration of moisture through the external protective material (encapsulant or seal) or along the interface between the external p

12、rotective material and the metallic conductors which pass through it. The stress usually activates the same failure mechanisms as the “85/85” Steady-State Humidity Life Test (JEDEC Standard No. 22-A101). 2 Apparatus The test requires a pressure chamber capable of maintaining a specified temperature

13、and relative humidity continuously, while providing electrical connections to the devices under test in a specified biasing configuration. 2.1 Controlled conditions The chamber must be capable of providing controlled conditions of pressure, temperature and relative humidity during ramp-up to, and ra

14、mp-down from the specified test conditions. Calibration records shall verify that the equipment avoids condensation on devices under test (DUTs) hotter than 50 C during ramp-up and ramp-down for conditions of maximum thermal mass loading and minimum (zero) DUT power dissipation. Calibration records

15、shall verify that, for steady state conditions and maximum thermal mass loading, test conditions are maintained within the tolerances specified in 3.1. 2.2 Temperature profile A permanent record of the temperature profile for each test cycle is recommended, so that the validity of the stress can be

16、verified. 2.3 Devices under stress Devices under stress must be physically located to minimize temperature gradients. Devices under stress shall be no closer than 3 cm from internal chamber surfaces, and must not be subjected to direct radiant heat from heaters. Boards on which devices are mounted s

17、hould be oriented to minimize interference with vapor circulation. JEDEC Standard No. 22-A110E Page 2 Test Method A110E (Revision of A110D) 2 Apparatus (contd) 2.4 Minimize release of contamination Care must be exercised in the choice of board and socket materials, to minimize release of contaminati

18、on and to minimize degradation due to corrosion and other mechanisms. 2.5 Ionic contamination Ionic contamination of the test apparatus (card cage, test boards, sockets, wiring storage containers, etc.) shall be controlled to avoid test artifacts. 2.6 De-ionized water De-ionized water with a minimum

19、 resistivity of 1 M-cm at room temperature shall be used. 3 Test conditions Test conditions consist of a temperature, relative humidity, and duration in conjunction with an electrical bias configuration specific to the device. 3.1 Temperature, relative humidity and duration Temperature1dry bulb C Re

20、lative Humidity1% Temperature2wet bulb, C Vapor Pressure2kPa (psia) Duration3hours 130 2 85 5 124.7 230 (33.3) 96 +2/-0 110 2 85 5 105.2 122 (17.7) 264 +2/-0 NOTE 1 Tolerances apply to the entire useable test area. NOTE 2 For information only. NOTE 3 The test conditions are to be applied continuousl

21、y except during any interim readouts. NOTE 4 For interim readouts, devices should be returned to stress within the time specified in 4.5. NOTE 5 For parts that reach absorption equilibrium in 24 hours or less, the HAST test is equivalent to at least 1000 hours at 85 C/85 %RH. For parts that require

22、more than 24 hours to reach equilibrium at the specified HAST condition, the time should be extended to allow parts to reach equilibrium. NOTE 6 Caution: For plastic-encapsulated microcircuits, it is known that moisture reduces the effective glass transition temperature of the molding compound. Stre

23、ss temperatures above the effective glass transition temperature may lead to failure mechanisms unrelated to standard 85C/85% RH stress. JEDEC Standard No. 22-A110E Page 3 Test Method A110E (Revision of A110D) 3 Test conditions (contd) 3.2 Biasing guidelines Apply bias according to the following gui

24、delines: a) Minimize power dissipation. b) Alternate pin bias as much as possible. c) Distribute potential differences across chip metallization as much as possible. d) Maximize voltage within operating range. NOTE The priority of the above guidelines depends on mechanism and specific device charact

25、eristics. e) Either of two kinds of bias can be used to satisfy these guidelines, whichever is more severe: 1) Continuous bias - The dc bias shall be applied continuously. Continuous bias is more severe than cycled bias when the die temperature is 10 C higher than the chamber ambient temperature or,

26、 if the die temperature is not known when the heat dissipation of the DUT is less than 200 mW. If the heat dissipation of the DUT exceeds 200 mW, then the die temperature should be calculated. If the die temperature exceeds the chamber ambient temperature by more than 5 C then the die temperature ri

27、se above the chamber ambient should be included in reports of test results since acceleration of failure mechanisms will be affected. 2) Cycled bias - The dc voltage applied to the devices under test shall be periodically interrupted with an appropriate frequency and duty cycle. If the biasing confi

28、guration results in a temperature rise above the chamber ambient, Tja, exceeding 10 C, then cycled bias, when optimized for a specific device type, will be more severe than continuous bias. Heating as a result of power dissipation tends to drive moisture away from the die and thereby hinders moistur

29、e-related failure mechanisms. Cycled bias permits moisture collection on the die during the off periods when device power dissipation does not occur. Cycling the DUT bias with a 50% duty cycle is optimal for most plastic encapsulated microcircuits. The period of the cycled stress should be 2 hours f

30、or packages 2 mm in thickness and 30 minutes for packages 2 mm in thickness. The die temperature, as calculated on the basis of the known thermal impedance and dissipation should be quoted with the results whenever it exceeds the chamber ambient by 5 C or more. JEDEC Standard No. 22-A110E Page 4 Tes

31、t Method A110E (Revision of A110D) 3.2 Biasing guidelines (contd) 3.2.1 Choosing and reporting Criteria for choosing continuous or cyclical bias, and whether or not to report the amount by which the die temperature exceeds the chamber ambient temperature, are summarized in the following table: Tja C

32、yclical Bias? Report Tja ? Tja 5 C, or Power per DUT 200 mW No No (Tja 5 C or Power per DUT 200 mW), and Tja 10 C No Yes Tja 10 C Yes Yes 4 Procedure The test devices shall be mounted in a manner that exposes them to a specified condition of temperature and humidity with a specified electrical biasi

33、ng condition. Exposure of devices to excessively hot, dry ambient or conditions that result in condensation on devices and electrical fixtures shall be avoided, particularly during ramp-up and ramp-down. 4.1 Ramp-up The time to reach stable temperature and relative humidity conditions should be less

34、 than 3 hours. Condensation shall be avoided by ensuring that the test chamber (dry bulb) temperature exceeds the wet-bulb temperature at all times, and that the rate of ramp up shall not be faster than a rate which ensures that the temperature of any DUT does not lag below the wet bulb temperature.

35、 The dry- and wet-bulb temperature set points shall be maintained so that the relative humidity is not less than 50% after significant heating begins. In a dry laboratory, the chamber ambient may initially be drier than this. JEDEC Standard No. 22-A110E Page 5 Test Method A110E (Revision of A110D) 4

36、 Procedure (contd) 4.2 Ramp-down The first part of ramp-down to a slightly positive gauge pressure (a wet bulb temperature of about 104 C) shall be long enough to avoid test artifacts due to rapid depressurization but should be less than 3 hours. The second part of ramp-down from a wet bulb temperat

37、ure of 104 C to room temperature shall occur with the chamber vented. There is no time restriction, and forced cooling of the vessel is permitted. Condensation on devices shall be avoided in both parts of the ramp down by ensuring that the test chamber (dry bulb) temperature exceeds the wet-bulb tem

38、perature at all times. Ramp-down should maintain the moisture content of the molding compound encapsulating the die. Therefore, the relative humidity shall not be less than 50% during the first part of the ramp down, paragraph 1 of 4.2. 4.3 Test Clock The test clock starts when the temperature and r

39、elative humidity reach the set points, and stops at the beginning of ramp-down. 4.4 Bias Bias application during ramp-up and ramp-down is optional. Bias should be verified after devices are loaded, prior to the start of the test clock. Bias should also be verified after the test clock stops, but bef

40、ore devices are removed from the chamber. NOTE It is recommended that current limiting resistor(s) be placed in the test setup to prevent test board or DUT damage in case a short develops during the test. 4.5 Readout Electrical test shall be performed not later than 48 hours after the end of ramp-do

41、wn. Note: For intermediate readouts, devices shall be returned to stress within 96 hours of the end of ramp down. The rate of moisture loss from devices after removal from the chamber can be reduced by placing the devices in sealed moisture barrier bags (without desiccant). When devices are placed i

42、n sealed bags, the “test window clock” runs at 1/3 of the rate of devices exposed to the laboratory ambient. Thus the test window can be extended to as much as 144 hours, and the time to return to stress to as much as 288 hours by enclosing the devices in moisture-proof bags. NOTE 1 The electrical t

43、est parameters should be chosen to preserve any defect (i.e., by limiting the applied test current). NOTE 2 Additional time-to-test delay or return-to-stress delay time may be allowed if justified by technical data 4.6 Handling Suitable hand-covering shall be used to handle devices, boards and fixtu

44、res. Contamination control is important in any highly-accelerated moisture stress test. JEDEC Standard No. 22-A110E Page 6 Test Method A110E (Revision of A110D) 5 Failure criteria A device will be considered to have failed the Highly- Accelerated Temperature and Humidity Stress Test if parametric li

45、mits are exceeded, or if functionality cannot be demonstrated under nominal and worst-case conditions as specified in the applicable procurement document or data sheet. 6 Safety Follow equipment manufacturers recommendations and local safety regulations. 7 Summary The following details shall be spec

46、ified in the applicable procurement document: a) Test duration. b) Temperature. c) Measurements after test. d) Biasing configuration. e) Temperature of die during test if it is more than 5 C above the chamber ambient. f) Frequency and duty cycle of bias if cycled bias is to be used. JEDEC Standard N

47、o. 22-A110E Page 7 Test Method A110E (Revision of A110D) Annex A (informative) Differences between JESD22-A110E and its predecessors The following list briefly describes most of the changes made to the entries that appear in this publication, JESD22-A110E, compared to its predecessor, JESD22-A110D (

48、November 2010). If the change to a concept involves any words added or deleted, it is included. Punctuation changes may not be included. Clause Description of change 2.6 Change megohm to M 4.1 Change from shall to should 4.2 Change “shall not exceed” to “should be less than” A.1 Differences between

49、JESD22-A110D and JESD22-A110C (January 2009) Clause Description of change 4.5 Added Note 1 and Note 2. A.2 Differences between JESD22-A110C and JESD22-A110-B Clause Description of change 4.4 Added note. JEDEC Standard No. 22-A110E Page 8 Test Method A110E (Revision of A110D) Rev. 9/02 Standard Improvement Form JEDEC JESD22-A110E The purpose of this form is to provide the Technical Committees of JEDEC with input from the industry regarding usage of the subject standard. Individuals or companies are invited to submit comments to JEDEC