JEDEC JESD22-A115C-2010 Electrostatic Discharge (ESD) Sensitivity Testing Machine Model (MM).pdf

1、JEDEC STANDARD Electrostatic Discharge (ESD) Sensitivity Testing, Machine Model (MM) JESD22-A115C (Revision of JESD22-A115B, March 2010) NOVEMBER 2010 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved thro

2、ugh the JEDEC Board of Directors level and subsequently reviewed and approved by the JEDEC legal counsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improve

3、ment of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. JEDEC standards and publications are adopted without regard to whether

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5、publications represents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may be further processed and ultimately become an ANSI standar

6、d. No claims to be in conformance with this standard may be made unless all requirements stated in the standard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC at the address below, or call (703) 907-7559 or www

7、.jedec.org Published by JEDEC Solid State Technology Association 2010 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 This document may be downloaded free of charge; however JEDEC retains the copyright on this material. By downloading this file the individual agrees not to charge for

8、 or resell the resulting material. PRICE: Refer to www.jedec.org Printed in the U.S.A. All rights reserved PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by JEDEC and may not be reproduced without permission. Organizations may obtain permission to reproduce a limited number of copies thr

9、ough entering into a license agreement. For information, contact: JEDEC Solid State Technology Association 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 or call (703) 907-7559 SPECIAL NOTE JESD22-A115 is a reference document; it is not a requirement per JESD47 (Stress Test Driven Q

10、ualification of Integrated Circuits). Machine Model as described in JESD22-A115 should not be used as a requirement for integrated circuit ESD qualification. Only HBM and CDM are the necessary ESD qualification test methods as specified in JESD47. JEDEC Standard No. 22-A115C Page 1 Test Method A115C

11、 (Revision of Test Method A115B) TEST METHOD A115B ELECTROSTATIC DISCHARGE (ESD) SENSITIVITY TESTING, MACHINE MODEL (MM) (From JEDEC Board Ballot JCB-97-10, and JCB-10-13, and JCB-10-60, formulated under the cognizance of JC-14.1 Committee on Reliability Test Methods for Packaged Devices.) 1 Scope T

12、his method establishes a standard procedure for testing microcircuits using an electrostatic discharge (ESD) model known commonly in the industry as the Machine Model (MM). The objective is to provide reliable, repeatable MM ESD test results. There is limited data supporting the ability of this mode

13、l to simulate discharges of machinery or to establish manufacturing handling practices. However, the model is useful for producing human-body model (HBM)-like ESD effects at lower voltages and for failure mode determination. The method produces results with are closely related to HBM and produces si

14、milar failure modes. 2 Apparatus This test method requires the following equipment. 2.1 Simulator An ESD Pulse Simulator and a Device Under Test (DUT) socket equivalent to the circuit of Figure 1. The simulator must be capable of supplying pulses with the characteristics required by Figure 2 and Fig

15、ure 3. 2.2 Oscilloscope The oscilloscope and amplifier combination shall have a 350 MHz minimum single-shot bandwidth and a visual writing speed of 4 cm/ns minimum. 2.3 Current probe The current probe shall have a minimum pulse-current bandwidth of 350 MHz. A current probe (transformer and cable wit

16、h a nominal length of 1 meter) with a 1 GHz bandwidth and a current rating of 12 amperes maximum pulse-current is recommended. 2.4 Evaluation Loads An 18 AWG tinned copper wire is recommended for the short waveform verification test. The lead length should be as short as practicable to span the dist

17、ance between the two farthest pins in the socket while passing through the current probe. The ends of the 18 AWG wire may be ground to a point where clearance is needed to make contact on fine pitch socket pins. JEDEC Standard No. 22-A115C Page 2 Test Method A115B (Revision of Test Method A115B) 2 A

18、pparatus (contd) 2.4 Evaluation Loads (contd) A 500 ohm +/-1%, 1000 volt, low inductance resistor shall be used for initial system checkout and periodic system recalibration. Figure 1 Typical equivalent MM ESD circuit NOTE 1 The performance of any simulator is influenced by its parasitic capacitance

19、 and inductance. NOTE 2 Precautions must be taken in tester design to avoid recharge transients and multiple pulses. NOTE 3 R2, used for initial equipment qualification and requalification as specified in 3.1, shall be a low inductance, 1000 volt, 500 ohm resistor with +/-1% tolerance. NOTE 4 Stacki

20、ng of DUT socket adaptors (piggybacking) is allowed only if the waveforms can be verified to meet the specifications in Table 1. NOTE 5 Reversal of terminal A and B to achieve dual polarity is not permitted. NOTE 6 S2 should be closed 10 to 100 milliseconds after the pulse delivery period to ensure

21、the DUT socket is not left in a charged state. NOTE 7 C1, 200 pF +/- 10%. JEDEC Standard No. 22-A115C Page 3 Test Method A115C (Revision of Test Method A115B) 2 Apparatus (contd) Figure 2 Current Waveform through a shorting wire, 400 volt discharge Figure 3 Current waveform through a 500 ohm resisto

22、r, 400 volt discharge JEDEC Standard No. 22-A115C Page 4 Test Method A115B (Revision of Test Method A115B) 3 Qualification, calibration, and waveform verification 3.1 Equipment qualification Equipment calibration must be performed during initial acceptance testing. Recalibration is required whenever

23、 equipment repairs are made that may affect the waveform and a minimum of every 12 months. The tester must meet the requirements of Table 1 and Figure 2 at all voltage levels using the shorting wire and at the 400 volt level with the 500 ohm resistor (see Figure 3). The waveform measurements during

24、calibration shall be made using the worst-case pin on the highest pin count board with a positive mechanical clamp socket. (Machine repeatability should be verified during initial equipment acceptance by performing a minimum of 5 consecutive positive and a minimum of 5 consecutive negative waveforms

25、 at a voltage level in Table 1.) The high-voltage relays and associated high-voltage circuitry shall be tested by the user of computer-controlled systems per the equipment manufacturers instructions (system diagnostics). This test will check for any open or short relays. Table 1 Waveform specificati

26、on Voltage Level (V) Positive Ipeak for Short, Ips1 (A) Positive Ipeak for 500 Ohm* Ipr (A) Current at 100 ns for 500 Ohm* I100 (A) Maximum Ringing Current, IR(A) Resonance Frequency for Short, FR (1/tfr) (Mhz) 100 1.5 - 2.0 N/A N/A Ips1 x 30% 11 - 16 200 2.8 - 3.8 N/A N/A Ips1 x 30% 11 - 16 400 5.8

27、 - 8.0 I100 x 4.5 maximum 0.29+/-20% Ips1 x 30% 11 - 16 * The 500 ohm load is used only during Equipment Qualification as specified in 3.1. 3.1.1 Safety Training During initial equipment set-up, the safety engineer or applicable safety representative, shall inspect the equipment in its operating loc

28、ation to ensure that the equipment is not operated in a combustible (hazardous) environment. Additionally, all personnel shall receive system operational training and electrical safety training prior to using the equipment. JEDEC Standard No. 22-A115C Page 5 Test Method A115C (Revision of Test Metho

29、d A115B) 3 Qualification, calibration, and waveform verification (contd) 3.2 Worst-case pin The worst-case pin combination for each socket and DUT board shall be identified and documented. It is recommended that the manufacturers supply the worst-case pin data with each DUT board. The pin combinatio

30、n with the waveform closest to the limits (see Table 1) shall be designated for waveform verification. The worst-case pin combination shall be identified by the following procedure. 3.2.1 For each test socket, identify the socket pin with the shortest wiring path from the pulse generating circuit to

31、 the test socket. Connect this pin to Terminal B (where it will remain the referenced pin throughout the worst case pin search) and connect one of the remaining pins to Terminal A. Attach a shorting wire between these pins with the current probe around the shorting wire, as close to Terminal B as pr

32、acticable. 3.2.2 Apply a positive 400 volt pulse and a negative 400 volt pulse and verify that the waveform meets the requirements defined in Table 1 for both positive and negative pulses. 3.2.3 Repeat steps 3.2.1 and 3.2.2 until all socket pins have been evaluated. 3.2.4 Determine the worst-case pi

33、n pair (within the limits and closest to the minimum or maximum parameter values as specified in Table 1) to be used for future waveform verification. 3.2.5 For initial board check-out, connect a 500 ohm resistor between the worst-case pins previously identified with the shorting wire in step 3.2.4.

34、 Apply a positive and negative 400 volt pulse and verify that the waveform meets the requirements defined in Table 1. NOTE In case the test socket/test board has already been characterized for worst-case pin on HBM, then that pin combination is acceptable for use with MM waveform verification. As an

35、 alternative to the worst-case pin search, the reference pin pair may be identified for each test socket of each test fixture. The reference pin combination shall be identified by determining the socket pin with the shortest wiring path from the pulse generating circuit to the test socket. Connect t

36、his pin to Terminal B and then connect the socket pin with the longest wiring path from the pulse generating circuit to the test socket to Terminal A (normally provided by the manufacturer). Attach a shorting wire between these pins with the current probe around the shorting wire. Follow the procedu

37、re in step 3.2.2. For the initial board check-out connect a 500 ohm resistor between the reference pins. Apply a positive and negative 400 volt pulse and verify that the waveform meets the parameters in Table 1. JEDEC Standard No. 22-A115C Page 6 Test Method A115B (Revision of Test Method A115B) 3 Q

38、ualification, calibration, and waveform verification (contd) 3.3 Waveform verification The waveform verification shall be performed at the beginning of each shift a tester is operated and when a socket/DUT board is changed. If at any time the waveforms do not meet the requirements defined in Figure

39、1 and Table 1 at the 400 volt level, the testing shall be halted until the waveform is in compliance. Additionally, the system diagnostics test as defined in 3.1 for automated systems shall be performed prior to the beginning of each shift testing is done. The period between waveform checks may be e

40、xtended providing test data supports the increased interval. In case the waveform no longer meets the limits in Table 1, all ESD testing performed after the previous satisfactory waveform check will be considered invalid. 3.3.1 With the required DUT socket installed and with no part in the socket, a

41、ttach a shorting wire in the DUT socket such that the worst-case pins are connected between Terminal A and Terminal B as shown in Figure 2. Place the current probe around the shorting wire. 3.3.2 Initiate a positive pulse at the 400 volt level per Table 1 and Figure 2. Verify that all parameters mee

42、t the limits specified in Table 1 and Figure 1. 3.3.3 Initiate a negative pulse at the 400 volt level per Table 1. Verify that all parameters meet the limits specified in Table 1 and Figure 1. 4 Characterization The devices used for characterization testing must have completed all normal manufacturi

43、ng operations. 4.1 Prior to ESD testing, dc parametric and functional testing at room temperature and, if applicable, high temperature shall be performed on all devices submitted for ESD testing. The test devices shall meet device data sheet requirements for these parameters. 4.2 A sample of 3 devic

44、es for each voltage level shall be characterized for the device ESD failure threshold using the voltage steps shown in Table 1. Finer voltage steps may optionally be used to obtain a more accurate measure of the failure threshold. ESD Testing should begin at the lowest step in Table 1. The ESD test

45、shall be performed at room temperature. 4.3 Each sample of 3 devices shall be stressed at one voltage level using 1 positive and 1 negative pulses with a minimum of 0.5 second between pulses per pin for all pin combinations specified in Table 2. It is permitted to use a separate sample of 3 devices

46、for each pin combination specified in Table 2. It is permitted to use the same sample (3) at the next higher voltage stress level if all parts pass the failure criteria specified in clause 5 after ESD exposure to a specified voltage level. JEDEC Standard No. 22-A115C Page 7 Test Method A115C (Revisi

47、on of Test Method A115B) 4 Characterization (contd) 4.4 Pin combinations, the pin combinations to be used are given in Table 2. The actual number of pin combinations depends on the number of power pin groups. Like named power pins (VCC1, VCC2, VSS1, VSS2, GND, etc.) that are directly connected by me

48、tal (inside the package) may be tied together and treated as one pin for Terminal B connection. Otherwise, each power pin must be treated as a separate power pin. Programming pins that do not draw current should be considered as I/O pins (example: Vpp pins on memory devices). Active discrete devices

49、 (FETs, transistors, etc.) shall be tested using all possible pin-pair combinations (one pin connected to Terminal A, another pin connected to Terminal B) regardless of pin name or function. All pins configured as “no connect“ pins shall be verified as “no-connect” and left open (floating) at all times. Pins labeled “no-connect”, that in fact are connected, shall be tested as non-supply pins. Table 2 Pin Combinations for Integrated Circuits Pin Combination Connect Individually to Terminal A Connect to Terminal B (Ground) Floating Pins (unconnected) 1 All pins one at a