JEDEC JESD223D-2018 Universal Flash Storage Host Controller Interface (UFSHCI) Version 3 0.pdf

1、 JEDEC STANDARD Universal Flash Storage Host Controller Interface (UFSHCI) Version 3.0 JESD223D (Revision of JESD223C, March 2016) JANUARY 2018 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the

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9、0 South Arlington, VA 22201-2107 or refer to www.jedec.org under Standards-Documents/Copyright Information. JEDEC Standard No. 223D -i- UNIVERSAL FLASH STORAGE HOST CONTROLLER INTERFACE (UFSHCI) Contents 1 Scope . 1 2 Normative Reference . 1 3 Acronyms, Terms and Definitions, Keywords, and Conventio

10、ns 2 4 Architectural Overview . 5 4.1 Outside of Scope 5 4.2 Interface Architecture 6 4.3 Transfer Request Interface . 8 4.4 Limitations . 9 5 UFS Host Controller Register Interface 9 5.1 Register Map 10 5.2 Host Controller Capabilities Registers . 11 5.2.1 Offset 00h: CAP Controller Capabilities 11

11、 5.2.2 Offset 08h: VER UFS Version . 12 5.2.3 Offset 10h: HCPID Host Controller Identification Descriptor Product ID 12 5.2.4 Offset 14h: HCMID Host Controller Identification Descriptor Manufacturer ID . 12 5.2.5 Offset 18h: AHIT Auto-Hibernate Idle Timer 13 5.3 Operation and Runtime Registers 14 5.

12、3.1 Offset 20h: IS Interrupt Status 14 5.3.2 Offset 24h: IE Interrupt Enable . 16 5.3.3 Offset 30h: HCS Host Controller Status . 17 5.3.4 Offset 34h: HCE Host Controller Enable . 18 5.3.5 Offset 38h: UECPA Host UIC Error Code PHY Adapter Layer 19 5.3.6 Offset 3Ch: UECDL Host UIC Error Code Data Link

13、 Layer . 19 5.3.7 Offset 40h: UECN Host UIC Error Code Network Layer 20 5.3.8 Offset 44h: UECT Host UIC Error Code Transport Layer . 20 5.3.9 Offset 48h: UECDME Host UIC Error Code . 20 5.3.10 Offset 4Ch: UTRIACR UTP Transfer Request Interrupt Aggregation Control Register . 21 5.4 UTP Transfer Reque

14、st Registers 22 5.4.1 Offset 50h: UTRLBA UTP Transfer Request List Base Address . 22 5.4.2 Offset 54h: UTRLBAU UTP Transfer Request List Base Address Upper 32-bits . 22 5.4.3 Offset 58h: UTRLDBR UTP Transfer Request List Door Bell Register 23 5.4.4 Offset 5Ch: UTRLCLR UTP Transfer Request List CLear

15、 Register . 23 5.4.5 Offset 60h: UTRLRSR UTP Transfer Request List Run Stop Register . 23 5.4.6 Offset 64h: UTRLCNR UTP Transfer Request List Completion Notification Register 24 5.5 UTP Task Management Registers . 25 5.5.1 Offset 70h: UTMRLBA UTP Task Management Request List Base Address . 25 5.5.2

16、Offset 74h: UTMRLBAU UTP Task Management Request List Base Address Upper 32-bits . 25 5.5.3 Offset 78h: UTMRLDBR UTP Task Management Request List Door Bell Register 25 5.5.4 Offset 7Ch: UTMRLCLR UTP Task Management Request List CLear Register 26 5.5.5 Offset 80h: UTMRLRSR UTP Task Management Request

17、 List Run Stop Register 26 5.6 UIC Command Registers . 27 5.6.1 Offset 90h: UICCMD UIC Command 27 5.6.2 Offset 94h: UICCMDARG1 UIC Command Argument 1 . 28 5.6.3 Offset 98h: UICCMDARG2 UIC Command Argument 2 . 29 5.6.4 Offset 9Ch: UICCMDARG3 UIC Command Argument 3 . 30 5.6.5 Attributes for Local L2 T

18、imers 30 JEDEC Standard No. 223D -ii- Contents (contd) 5.7 Vendor Specific Registers 31 5.7.1 Offset C0h to FFh: VS Vendor Specific . 31 5.8 Crypto Registers 31 5.8.1 Offset 100h: CCAP Crypto Capability . 31 5.8.2 x-CRYPTOCAP Crypto Capability X 32 5.8.3 x-CRYPTOCFG Crypto Configuration X 33 6 Data

19、structures . 35 6.1 UTP Transfer Request List 35 6.1.1 UTP Transfer Request Descriptor 35 6.1.2 UTP Command Descriptor 39 6.2 UTP Task Management Request List 41 6.2.1 UTP Task Management Request Descriptor 41 6.3 Key Organization for Cryptographic Algorithms 43 6.3.1 AES-XTS . 43 6.3.2 Bitlocker-AE

20、S-CBC 45 6.3.3 AES-ECB . 46 6.3.4 ESSIV-AES-CBC 47 7 Theory of Operation 47 7.1 Host Controller Configuration and Control . 48 7.1.1 Host Controller Initialization . 48 7.1.2 Configuration and control 50 7.1.3 CRYPTOCFG Configuration Procedure . 50 7.2 Data Transfer Operation 51 7.2.1 Basic Steps wh

21、en Building a UTP Transfer Request . 52 7.2.2 UPIU Processing 53 7.2.3 Processing UTP Transfer Request Completion . 55 7.3 Task Management Function . 57 7.3.1 Basic Steps when Building a UTP Task Management Request . 57 7.3.2 Processing UTP Task Management Completion . 57 7.4 UIC Power Mode Change 5

22、8 7.5 UFSHCI Internal Rules 59 7.5.1 Command Processing Order 60 7.5.2 RTT Processing Rules 61 7.5.3 Data Unit Processing Order for Cryptographic operations 61 8 error reporting and handling 62 8.1 Error Types 62 8.1.1 System Bus Error . 62 8.1.2 UIC Error . 62 8.1.3 UIC Command Error 62 8.1.4 UTP E

23、rror 63 8.1.5 Host controller Fatal Error . 63 8.1.6 Device Error . 63 8.1.7 Hibernate Enter/Exit Error . 64 8.2 Error Handling . 64 8.2.1 System Bus Error Handling . 64 8.2.2 UIC Error Handling . 65 8.2.3 UIC Command Error Handling 65 8.2.4 UTP Error Handling . 66 JEDEC Standard No. 223D -iii- Cont

24、ents (contd) 8.2.5 Host Controller Error Handling . 66 8.2.6 Device Error Handling . 66 8.2.7 Hibernate Enter/Exit Error Handling . 66 9 Encryption ENGINE DETAILS (Informative) . 67 9.1 AES-XTS . 67 9.1.1 Overview 67 9.1.2 Data Unit Size 67 9.1.3 Tweak 68 9.2 Bitlocker AES-CBC . 68 9.2.1 Background

25、68 9.2.2 Overview 69 9.2.3 Sector (Data Unit) Size S . 69 9.2.4 Sector Offset O 69 9.2.5 Sector Initialization Vector (IV) 70 9.2.6 Encryption / Decryption . 70 9.3 AES-ECB . 70 9.3.1 Overview 70 9.4 ESSIV-AES-CBC 70 9.4.1 Background 70 9.4.2 Data Unit Size 70 9.4.3 Sector Number (SN) 71 9.4.4 Initi

26、alization Vector (IV) . 71 9.4.5 Encryption / Decryption . 71 Figures Figure 1 UFS Architecture Overview 5 Figure 2 General architecture of UFS Host Controller Interface. 6 Figure 3 A conceptual block diagram of UFS host system 8 Figure 4 x-CRYPTOCFG Array Entry Layout 34 Figure 5 UTP Transfer Reque

27、st Descriptor . 35 Figure 6 UTP Command Descriptor (UCD) 39 Figure 7 Data structure for Physical Region Description Table 40 Figure 8 UTP Task Management Request Descriptor. 41 Figure 9 AES128-XTS Key Layout . 43 Figure 10 AES192-XTS Key Layout . 44 Figure 11 AES256-XTS Key Layout . 44 Figure 12 AES

28、128-CBC Key Layout 45 Figure 13 AES256-CBC Key Layout 45 Figure 14 AES128-ECB Key Layout . 46 Figure 15 AES256-ECB Key Layout . 46 Figure 16 Host controller link startup sequence 49 Figure 17 UIC Power mode change . 59 Figure 18 Command processing order . 60 Figure 19 Byte Order For Data Unit Proces

29、sing in Cryptographic operations 61 Figure 20 AES-XTS Encryption 67 Figure 21 Bitlocker AES-CBC Encryption 69 Figure 22 IV Derivation from Sector Offset 70 Figure 23 AES-ECB Encryption 70 Figure 24 ESSIV-AES-CBC Encryption . 71 JEDEC Standard No. 223D -iv- JEDEC Standard No. 223D Page 1 UNIVERSAL FL

30、ASH STORAGE HOST CONTROLLER INTERFACE (UFSHCI) (From JEDEC Board ballot JCB-17-42, formulated under the cognizance of the JC-64.1 Subcommittee on Electrical Specifications and Command Protocols (Item 205.06).) 1 Scope This standard describes a functional specification of the Host Controller Interfac

31、e (HCI) for Universal Flash Storage (UFS). The objective of UFSHCI is to provide a uniform interface method of accessing the UFS hardware capabilities so that a standard/common Driver can be provided for the Host Controller. The common Driver would work with UFS host controller from any vendor. This

32、 standard includes a description of the hardware/software interface between system software and the host controller hardware. It is intended for hardware designers, system builders and software developers. This standard is a companion document to UFS, Universal Flash Storage (UFS). The reader is ass

33、umed to be familiar with UFS, MIPI-UNIPRO, and MIPI-M-PHY. Clause 4 provides a brief overview of the architectural overview of UFS. Clause 5 describes the register interface of UFSHCI. Clause 6 describes the data structure used by UFSHCI. Clause 7 provides a theory of operation for UFSHCI. Clause 8

34、describes the error recovery process for UFSHCI. 2 Normative Reference The following normative documents contain provisions that, through reference in this text, constitute provisions of this standard. For dated references, subsequent amendments to, or revisions of, any of these publications do not

35、apply. However, parties to agreements based on this standard are encouraged to investigate the possibility of applying the most recent editions of the normative documents indicated. For undated references, the latest edition of the normative document referred to applies. MIPI-M-PHY, MIPI Alliance Sp

36、ecification for M-PHYSM, Version 4.1 MIPI-UniPro, MIPI Alliance Specification for Unified Protocol (UniProSM), Version 1.8 MIPI-DDB, MIPI Alliance Specification for Device Descriptor Block (DDB), Version SAM, INCITS T10 draft standard: SCSI Architecture Model 5 (SAM5), Revision 05, 19 May 2010 SPC,

37、INCITS T10 draft standard: SCSI Primary Commands 4 (SPC-4), Revision 27, 11 October 2010 SBC, INCITS T10 draft standard: SCSI Block Commands 3 (SBC3), Revision 24, 05 August 2010 UFS, JEDEC JESDxxxx, Universal Flash Storage (UFS 2.1) JEP, JEDEC JEP106, Standard Manufacturers Identification Code JEDE

38、C Standard No. 223D Page 2 3 Acronyms, Terms and Definitions, Keywords, and Conventions 3.1 Acronyms DID Device ID GB Gigabyte HCI Host Controller Interface KB Kilobyte LUN Logical Unit Number MIPI Mobile Industry Processor Interface MB Megabyte NA Not applicable PRDT Physical Region Description Tab

39、le UCD UTP Command Descriptor UFS Universal Flash Storage UPIU UFS Protocol Information Unit UTP UFS Transport Protocol UTRD UTP Transfer Request Descriptor UTMRD UTP Task Management Request Descriptor 3.2 Terms and Definitions Byte: An 8-bit data value with most significant bit labeled as bit 7 and

40、 least significant bit as bit 0. Device ID: The bus address of a UFS device. Doubleword: A 32-bit data value with most significant bit labeled as bit 31 and least significant bit as bit 0. Dword: A 32-bit data value, a Doubleword. Gigabyte(GB): 1,073,741,824 or 230 bytes. Host: An addressable device

41、 on the UFS bus which is usually the main CPU that hosts the UFS bus. Kilobyte(KB): 1024 or 210bytes. Logical Unit Number: A numeric value that identifies a logical unit within a device. Megabyte(MB): 1,048,576 or 220 bytes. Quadword: A 64-bit data value with most significant bit labeled as bit 63 a

42、nd least significant bit as 0. JEDEC Standard No. 223D Page 3 3.2 Terms and Definitions (contd) UFS Protocol Information Unit: Information transfer (communication) between a UFS host and device is done through messages which are called UFS Protocol Information Units. NOTE The messages are UFS define

43、d data structures that contain a number of sequentially addressed bytes arranged as various information fields. UTP Transfer Request Descriptor: A data structure in system memory that contains a UTP command and additional contextual information needed to carry out the command operation. NOTE The com

44、mand is limited to UFS adopted INCITS T10 draft standard command sets (see UFS), UFS native command set and Device Management function that uses UTP protocol. A UTP Transfer Request Descriptor is built by the host and is targeted at the attached UFS device. UTP Task Management Request Descriptor: A

45、data structure in system memory that contains a UTP Task Management Function and the additional contextual information needed to execute the function. NOTE A UTP Transfer Request Descriptor is built by the host and is executed by the attached UFS device. Unit: A bus device. Word: A 16-bit data value

46、 with most significant bit labeled as bit 15 and least significant bit as bit 0. zero-based value: A numeric value N (N 0) represented by N-1 3.3 Keywords Several keywords are used to differentiate levels of requirements and options, as follow: Expected A keyword used to describe the behavior of the

47、 hardware or software in the design models assumed by this standard. Other hardware and software design models may also be implemented. Ignored A keyword that describes bits, bytes, quad lets, or fields whose values are not checked by the recipient. Mandatory A keyword that indicates items required

48、to be implemented as defined by this standard. May A keyword that indicates flexibility of choice with no implied preference. Optional A keyword that describes features which are not required to be implemented by this standard. However, if any optional feature defined by the standard is implemented,

49、 it shall be implemented as defined by the standard. JEDEC Standard No. 223D Page 4 3.3 Keywords (contd) Reserved A keyword used to describe objectsbits, bytes, and fieldsor the code values assigned to these objects in cases where either the object or the code value is set aside for future standardization. Usage and interpretation may be specified by future extensions to this or other standards. A reserved object shall be zeroed or,