JEDEC JESD232A-2016 GRAPHICS DOUBLE DATA RATE (GDDR5X) SGRAM STANDARD.pdf

1、JEDEC SOLID STATE TECHNOLOGY ASSOCIATIONJESD232AAUGUST 2016JEDECSTANDARDGRAPHICS DOUBLE DATA RATE(GDDR5X) SGRAM STANDARD (Revision of JESD232, November 2015)NOTICEJEDEC standards and publications contain material that has been prepared, reviewed, andapproved through the JEDEC Board of Directors leve

2、l and subsequently reviewed and approvedby the JEDEC legal counsel.JEDEC standards and publications are designed to serve the public interest through eliminatingmisunderstandings between manufacturers and purchasers, facilitating interchangeability andimprovement of products, and assisting the purch

3、aser in selecting and obtaining with minimumdelay the proper product for use by those other than JEDEC members, whether the standard is tobe used either domestically or internationally.JEDEC standards and publications are adopted without regard to whether or not their adoptionmay involve patents or

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5、ct specification and application, principally from the solid state device manufacturerviewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard orpublication may be further processed and ultimately become an ANSI standard.No claims to be in conformance with this standard

6、 may be made unless all requirements stated in the standard are met.Inquiries, comments, and suggestions relative to the content of this JEDEC standard orpublication should be addressed to JEDEC at the address below, or call (703) 907-7559 orwww.jedec.orgPublished byJEDEC Solid State Technology Asso

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9、e agreement. For information, contact:JEDEC Solid State Technology Association3103 North 10th Street, Suite 240SArlington, Virginia 22201or call (703) 907-7559JEDEC Standard No. 232A-i-Contents1 SCOPE 12 GDDR5X SGRAM STANDARD OVERVIEW .22.1 Features 23 FUNCTIONAL DESCRIPTION .33.1 Functional Overvie

10、w 33.2 Signal State Terminology .43.3 Clocking .43.4 Addressing .73.5 Bank Groups 103.6 Address Bus Inversion (ABI) .123.7 Read and Write Data Bus Inversion (DBI) 133.8 Error Detection Code (EDC) . 153.9 VREFC and VREFD . 193.10 Temperature Sensor 223.11 Duty Cycle Corrector 234 MODE REGISTERS 244.1

11、 Mode Register 0 .264.2 Mode Register 1 .284.3 Mode Register 2 .304.4 Mode Register 3 .324.5 Mode Register 4 .334.6 Mode Register 5 354.7 Mode Register 6 364.8 Mode Register 7 .374.9 Mode Register 8 .394.10 Mode Register 9 .404.11 Mode Register 10 .404.12 Mode Register 11 .414.13 Mode Register 12 to

12、 14 .414.14 Mode Register 15 .425 DEVICE INITIALIZATION .435.1 Power-up Sequence 435.2 Initialization with Stable Power . 455.3 Vendor ID 466 TRAINING .486.1 Interface Training Sequence .486.2 Address Training 496.3 WCK2CK Training 506.3.1 WCK Alignment at Pin Mode 536.3.2 WCK Auto Synchronization .

13、536.3.3 WCK2CK Training Examples .536.3.4 Read and Write Latencies .556.4 READ Training 566.4.1 LDFF Command .576.4.2 RDTR Command 606.5 WRITE Training 616.5.1 WRTR Command .627 OPERATION .647.1 Commands 647.2 Command, Address And Write Data Input Timings 65JEDEC Standard No. 232A-ii-7.3 No Operatio

14、n (NOP) 657.4 Mode Register Set .667.5 Row Activation 677.6 Write (WOM)697.6.1 DQ Write Preamble 767.7 Write Lower And Upper Bytes (WOML/WOMU)767.8 Write Data Mask (WDM/WSM).787.9 READ 877.9.1 DQ Read Preamble .947.9.2 READ with RDQS Mode .957.10 Precharge 967.10.1 Auto Precharge .977.11 Refresh 977

15、.11.1 Refresh Command .977.11.2 Per-Bank Refresh Command 987.12 Self Refresh . 1017.12.1 Hibernate Self Refresh .1047.12.2 Partial Array Self Refresh .1057.13 Power-Down 1057.14 Low Frequency Modes .1077.15 Clock Frequency Change Sequence .1087.16 Command Truth Tables .1088 OPERATING CONDITIONS .112

16、8.1 Absolute Maximum Ratings 1128.2 Pad Capacitances 1128.3 Package Electrical Specification.1138.4 Package Thermal Characteristics 1138.5 Electrostatic Discharge Sensitivity Characteristics 1148.6 DC 16n prefetch architecture with 512 bit per array read or write access; burst length 16 DDR mode: Do

17、uble Data Rate (DDR) data (WCK); 8n prefetch architecture with 256 bit per array read or write access; burst length 8 16 internal banks 4 bank groups for tCCDL= 3 tCKand 4 tCK Programmable read latency: 5 to 36 tCK; programmable write latency: 1 to 7 tCK Write data mask function via address bus (sin

18、gle/double/quad byte mask) Data bus inversion (DBI) programmable CRC write latency = 7 to 14 tCK Low Power modes RDQS mode on EDC pins On-chip temperature sensor with read-out Auto precharge option for each burst access Auto refresh mode with per-bank refresh option Temperature sensor controlled sel

19、f refresh rate Optional digital tRASlockout On-die termination (ODT) for all high-speed inputs Pseudo open drain (POD-135) compatible outputs ODT and output driver strength auto-calibration with external resistor ZQ pin (120 ) Programmable termination and driver strength offsets Internal VREFfor dat

20、a inputs with programmable levels Selectable external or internal VREFfor address / command inputs Vendor ID for device identification Mirror function with MF pin IEEE 1149.1 compliant boundary scan 1.35 V supply voltage for device operation (VDD) and I/O interface (VDDQ) 1.8 V pump voltage (VPP) 19

21、0 ball BGA package4 Gb = 128 Mb x 32 ( 8 Mb x 32 x 16 banks) / 256 Mb x 16 (16 Mb x 16 x 16 banks)6 Gb = 192 Mb x 32 (12 Mb x 32 x 16 banks) / 384 Mb x 16 (24 Mb x 16 x 16 banks)8 Gb = 256 Mb x 32 (16 Mb x 32 x 16 banks) / 512 Mb x 16 (32 Mb x 16 x 16 banks)12 Gb = 384 Mb x 32 (24 Mb x 32 x 16 banks

22、) / 768 Mb x 16 (48 Mb x 16 x 16 banks)16 Gb = 512 Mb x 32 (32 Mb x 32 x 16 banks) / 1 Gb x 16 (64 Mb x 16 x 16 banks)JEDEC Standard No. 232APage 33FUNCTIONAL DESCRIPTION3.1 FUNCTIONAL OVERVIEWThe GDDR5X SGRAM is a high speed dynamic random-access memory designed for applications requiring high band

23、width. It is internally configured as 16-bank memory and contains the following number of bits:4 Gb has 4,294,967,296 bits 6 Gb has 6,442,450,944 bits 8 Gb has 8,589,934,592 bits 12 Gb has 12,884,901,888 bits 16 Gb has 17,179,869,184 bitsThe GDDR5X SGRAMs high-speed interface is optimized for point-

24、to-point connections to a host controller. On-die termination (ODT) is provided for all high-speed interface signals to eliminate the need for termination resistors in the system.The GDDR5X SGRAM supports two operating modes which mainly differ in the internal prefetch and DQ/DBI_n pin to WCK clock

25、frequency ratio. The operating mode is set by a mode register bit: In Quad Data Rate (QDR) mode the interface transfers four 32-bit wide data words per WCK clock cycle to/from the I/O pins. Corresponding to the 16-n prefetch a single write or read access consists of a 512 bit wide, two CK clock cycl

26、e data transfer at the internal memory core and sixteen corresponding 32 bit wide one-quarter WCK clock cycle data transfers to the I/O pins. In Double Data Rate (DDR) mode the interface transfers two 32-bit wide data words per WCK clock cycle to/from the I/O pins. Corresponding to the 8-n prefetch

27、a single write or read access consists of a 256 bit wide, two CK clock cycle data transfer at the internal memory core and eight corresponding 32 bit wide one-half WCK clock cycle data transfers to the I/O pins.Read and write accesses to the GDDR5X SGRAM are burst oriented; an access starts at a sel

28、ected location and consists of a total of sixteen data words in QDR mode and eight data words in DDR mode. Accesses begin with the registration of an ACTIVATE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVATE command and the next ris

29、ing CK_c edge are used to select the bank and the row to be accessed. The address bits registered coincident with the READ or WRITE command and the next rising CK_c edge are used to select the bank and the column location for the burst access.This standard includes all features and functionality req

30、uired for JEDEC GDDR5X SGRAM devices. Users benefit from knowing that any system design based on the required aspects of the standard are supported by all GDDR5X SGRAM vendors; conversely users seeking to use any superset specifications bear the responsibility to verify support with individual vendo

31、rs.JEDEC Standard No. 232APage 43.2 SIGNAL STATE TERMINOLOGYThe GDDR5X SGRAM will be operated in both ODT enable (terminated) and ODT disable (unterminated) modes. For highest data rates it is recommended to operate in the ODT enable mode. ODT disable mode is designed to reduce power and may operate

32、 at reduced data rates. There exist situations where ODT enable mode can not be guaranteed for a short period of time, for example during power-up.Four terminologies define the state of a device pin (GDDR5X SGRAM or controller) during operation. The state of the bus will be determined by the combina

33、tion of the device pins connected to the bus in the system. For example, with GDDR5X it is possible for the device pin to be tristated while the controller pin is High or ODT. In both cases the bus would be High if the ODT is enabled.Device pin signal level: High: a device pin drives the Logic “1” s

34、tate. Low: a device pin drives the Logic “0” state. High-Z: a device pin is tristate. ODT: a device pin terminates with ODT setting, which could be terminating or tristate depending on mode register setting.Bus signal level: High: one device on the bus is High and all other devices on bus are either

35、 ODT or High-Z. The voltage level on the bus would be nominally VDDQ. Low: one device on the bus is Low and all other devices on bus are either ODT or High-Z. The voltage level on the bus would be nominally VOL(DC) if ODT is enabled, or VSSQif High -Z. High-Z: all devices on the bus are High-Z. The

36、voltage level on bus is undefined as the bus is floating. ODT: at least one device on the bus is ODT and all others are High-Z. The voltage level on the bus would be nominally VDDQ.3.3 CLOCKINGThe GDDR5X SGRAM operates from a differential clock CK_t and CK_c. Commands are registered at every rising

37、edge of CK_t. Addresses are registered at every rising edge of CK_t and every rising edge of CK_c.The data interface uses two differential forwarded clocks WCK_t and WCK_c, each associated with two data bytes. WCK_t and WCK_c are continuously running and operate at twice the frequency of the command

38、/address clock (CK_t/CK_c). A PLL/DLL is associated with each WCK pair. The use of the PLL/DLL is mandatory in QDR mode and vendor specific in DDR mode. QDR mode uses a quad data rate data interface and a 16n-prefetch architecture for DQ/DBI_n, and a double data rate data interface and 8n-prefetch a

39、rchitecture for EDC. The PLL/DLL generates four equally spaced clock edges per WCK clock cycle. QDR means that four DQ/DBI_n data words per WCK cycle are registered at these internally generated clock edges. DDR means that two EDC data words per WCK cycle are registered at every second of these inte

40、rnally generated clock edges. DDR mode uses a double data rate data interface and an 8n-prefetch architecture for DQ/DBI_n/EDC. DDR means that the data is registered at every rising edge of WCK_t and rising edge of WCK_c.JEDEC Standard No. 232APage 53.3 CLOCKING (contd)Table 1 and Figure 1 illustrat

41、e the clock and interface signal relationship for both QDR and DDR operating modes.Figure 1 GDDR5X Clocking and Interface RelationshipTable 1 Example Clock and Interface Signal Frequency RelationshipPIN QDR MODE DDR MODE UNITCK_t, CK_c 1.5 1.5 GHzCommand 1.5 1.5 Gbps/pinAddress 3.0 3.0 Gbps/pinWCK_t

42、, WCK_c 3.0 3.0 GHzDQ, DBI_n 12.0 6.0 Gbps/pinEDC 6.0 6.0 Gbps/pinCK_cCK_tCOMMANDWCK_tWCK_cDQ, DBI_n(QDR Mode)DQ, DBI_n(DDR Mode)EDC(QDR + DDR Modes)ADDRESSNOTE 1 Figure 1 shows the relationship between the data rate of the buses and the clocks and is not a timing diagram.JEDEC Standard No. 232APage

43、 63.3 CLOCKING (contd)Figure 2 Block Diagram of an Example Clock SystemClock PhaseOscillatorQDADD/CMDADD/CMDDRAM DATA DQearly/lateReceiverD QWCKintDQDRAM PLL/DLLQDDQPhase detector/logicearly/late fromController GDDR5X SGRAMPLL/DLLclockData Tx/RxWCK_t/(3 GHz)CK_t/CK_c(1.5 GHz)CMD sampled by CK_t/CK_c

44、 as SDRADD sampled by CK_t/CK_c as DDRADD/CMD centered with CK_t/CK_ccalibration dataaccumulatorControllerClock PhaseController(QDR mode:corecoreQDR mode: 3.0 GHzD QWCK2CKAlignmentTo EDC pin/2WCK_cDDR mode: 1.5 GHz(DDR mode only)12 Gbps)(DDR mode:6 Gbps)QDcoreJEDEC Standard No. 232APage 73.4 ADDRESS

45、INGGDDR5X SGRAMs use a double data rate address scheme to reduce pins required on the device as shown in Table 2. The addresses should be provided in two parts; the first half is latched on the rising edge of CK_t along with the command pins such as RAS_n, CAS_n and WE_n; the second half is latched

46、on the next rising edge of CK_c.The use of DDR addressing allows all address values to be latched in at the same rate as the SDR commands. All addresses related to command access have been positioned for latching on the initial rising edge for faster decoding.The addressing includes support for 4 Gb

47、 to 16 Gb densities and both QDR and DDR operating modes as shown in Table 3. Table 2 Address PairsClock Address PinsRising CK_t BA3 BA2 BA1 BA0 A14 A12 A11 A10 A9 A8Rising CK_c A3 A4 A5 A2 A15 A13 A6 A0 A1 A7Table 3 Addressing SchemeDensity 4 Gb 6 Gb 8 Gb 12 Gb 16 GbI/O Configuration x32 x16 x32 x1

48、6 x32 x16 x32 x16 x32 x16Row address A0A12 A0A13 A0-A13 A0-A14 A0A13 A0A14 A0A14 A0A15 A0A14 A0A15Column address DQ15:0QDR Mode A0A5 A0A5 A0A5 A0A5 A0A5DDR Mode A0A6 A0A6 A0A6 A0A6 A0A6Column address DQ31:16QDR Mode A7,A9,A12A15 A7,A9,A12A15 A7,A9,A12A15 A7,A9,A12A15 A7,A9,A12A15DDR Mode A7,A9,A12A1

49、5,A6 A7,A9,A12A15,A6 A7,A9,A12A15,A6 A7,A9,A12A15,A6 A7,A9,A12A15,A6Bank address BA0BA3 BA0BA3 BA0BA3 BA0BA3 BA0BA3Autoprecharge A8 A8 A8 A8 A8Page Size 4K 2K 4K 2K 4K 2K 4K 2K 4K 2KRefresh 16K/32ms 16K/32ms 16K/32ms 16K/32ms 16K/32msRefresh period 1.9us 1.9us 1.9us 1.9us 1.9usNOTE 1 The burst order is fixed for Reads and Writes, and the GDDR5X SGRAM does not assign column address bits to distinguish between the UIs of a burst. A memory controller may internally assign such column address bits but these