JEDEC JESD237-2014 Reliability Qualification of Power Amplifier Modules.pdf

1、JEDEC STANDARD Reliability Qualification of Power Amplifier Modules JESD237 (Was previously released as JESD236 from February 25 to March 14, 2014) MARCH 2014 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and appro

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9、EDEC Solid State Technology Association 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 or refer to www.jedec.org under Standards-Documents/Copyright Information. JEDEC Standard No. 237 -i- RELIABILITY QUALIFICATION OF POWER AMPLIFIER MODULES Contents Page Foreword ii Introduction ii

10、 1 Scope 1 2 Reference documents 2 3 General requirements 2 3.1 Objective 2 3.2 Qualification family 2 3.3 Lot requirements 2 3.4 Production requirements 3 3.5 Reuseability of test samples 3 3.6 Definition of electrical test failure after stressing 3 3.7 Required stress tests for qualification 3 3.8

11、 Pass/Fail criteria 3 4 Qualification and requalification 4 4.1 Qualification of a new device 4 4.2 Requalification of a changed device 4 5 Qualification tests 5 5.1 General tests 5 5.2 Wearout reliability tests 5 5.3 Device qualification requirements 5 5.3.1 Life testing 6 5.3.2 Device specific tes

12、ts 7 5.4 Module qualification requirements 8 5.4.1 Module test descriptions 10 5.5 Reporting results 11 6 Explanatory comments regarding process/product changes 12 6.1 Changes requiring re-qualification 12 6.2 Changes that may not require re-qualification 13 6.3 Multiple family qualifications 13 6.4

13、 Guidelines for major process change selection of tests 14 Annex A (informative) Module temperature cycling description 15 JEDEC Standard No. 237 -ii- Foreword A unique application of semiconductor integrated circuits is within a module. Modules are sometimes referred to as a system-in-package (SIP)

14、 or hybrid. For the purpose of this document, we define a module as an assembly that integrates multiple semiconductor die within one package. Such a module is not restricted to semiconductors it can also contain passive devices that include components such as resistors, capacitors, inductors, filte

15、rs, and couplers that are either built-in to the substrate or added as Surface Mount Devices. Another unique aspect of a Laminate-based Power Amplifier Module (PAM) is the application of Compound Semiconductors. To further refine the classification of modules, we have specifically selected amplifica

16、tion to be the core function. But amplification is not necessarily the only function. Switching, power control, power detection, signal reception, filtering, and ESD suppression may be other functions performed within a module. Additionally, many of the functions may be employed over various frequen

17、cies and at various output power levels such that these functions are arranged in a parallel fashion within the module. A typical module application is a Power Amplifier Module (PAM) used at or near the “front-end” of a cellular phone or mobile device. PAMs are an enabling component of cell phones t

18、hat transmit signals with high efficiency, linearity, and reliability in a manner that is yet unmatched by monolithic devices. A typical PAM consists of a substrate, which may be a leadframe material, but is more commonly a ceramic or laminate multi-layer base. Upon the base, the aforementioned die

19、and components are mounted, and all components are encapsulated, using packaging materials, such as an epoxy, most commonly formed by a transfer mold process. Hermetic versions of PAMs utilize ceramic substrates and lids or caps that seal the various components within. Even though similar types of m

20、odules have been utilized for semiconductors in the past, the use of Compound Semiconductors, with a laminate substrate, for relatively high power dissipation wireless application at radio frequencies (RF) is seemingly unique. Introduction This standard is intended to identify a core set of qualific

21、ation tests that apply specifically for Power Amplifier Modules and their primary application in mobile devices such as cellular phones. There is a substantial amount of confusion and inefficiency in module reliability testing that is driven by: a) frequent attempts to apply silicon standards to com

22、pound semiconductor modules, and b) lack of ability to steer customers away from the silicon oriented standards that have dominated the industry for years. This standard is intended to describe specific stresses and failure mechanisms that are specific to compound semiconductors and power amplifier

23、modules. It is intended to establish more meaningful and efficient qualification testing. JEDEC Standard No. 237 Page 1 RELIABILITY QUALIFICATION OF POWER AMPLIFIER MODULES (From JEDEC Board Ballot JCB-14-09, formulated under the cognizance of the JC-14.7 Task Group on a Power Amplifier Module Stand

24、ard) 1 Scope This standard describes a baseline set of acceptance tests for use in qualifying power amplifier modules as an individual new product, a product family, or as products in a process which is being changed. These tests are capable of stimulating and precipitating semiconductor device, int

25、ernal component, laminate, and packaging failures. The objective is to precipitate failures in an accelerated manner compared to use conditions. Failure rate projections usually require larger sample sizes than are called out in qualification testing and durations or stresses which would exacerbate

26、normal wearout. For guidance on projecting failure rates, refer to JESD85 Methods for Calculating Failure Rates in Units of FITs. This qualification standard is not aimed at extreme use conditions such as military applications, automotive under-the-hood applications, or uncontrolled avionics environ

27、ments, nor does it address 2nd level reliability considerations, which are addressed in JEP150. This set of tests should not be used indiscriminately. Each qualification project should be examined for: a) Any potential new and unique failure mechanisms. b) Any situations where these tests/conditions

28、 may induce invalid or overstress failures. If it is known or suspected that failures either are due to new mechanisms or are uniquely induced by the severity of the test conditions, then the application of the test condition as stated is not recommended. Alternatively, new mechanisms or uniquely pr

29、oblematic stress levels should be addressed by building an understanding of the mechanism and its behavior with respect to accelerated stress conditions (Ref. JESD91 Method for Developing Acceleration Models for Electronic Component Failure Mechanisms.) Another alternative qualification method is de

30、scribed in JESD94 Application Specific Qualification using Knowledge Based Test Methodology. This technique involves establishing the (worst case) use conditions and tailoring the stress methods, stress levels, and durations to match the use conditions. Since the assembly is considered an integral p

31、art of the power amplifier module, this standard includes the applicable package-related stresses. However, if special consideration of assembly-level effects is necessary, then guidance from JEP150, Stress-Test-Driven Qualification of and Failure Mechanisms Associated with Assembled Solid State Sur

32、face-Mount Components, is recommended. JEDEC Standard No. 237 Page 2 2 Reference documents J-STD-020, Joint IPC/JEDEC Standard, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface-Mount Devices. JP-001, Foundry Process Qualification Guidelines (Wafer Fabrication Manufactur

33、ing Sites). JESD22 Series, Reliability Test Methods for Packaged Devices JESD46, Guidelines for User Notification of Product/process Changes by Semiconductor Suppliers. JESD47, Stress-Test-Driven Qualification of Integrated Circuits. JESD69, Information Requirements for the Qualification of Silicon

34、Devices. JESD74, Early Life Failure Rate Calculation Procedure for Electronic Components. JESD78, IC Latch-Up Test. JESD85, Methods for Calculating Failure Rates in Units of FITs. JESD86, Electrical Parameters Assessment. JESD94, Application Specific Qualification using Knowledge Based Test Methodol

35、ogy. JESD91, Methods for Developing Acceleration Models for Electronic Component Failure Mechanisms. JEP122, Failure Mechanisms and Models for Semiconductor Devices. JEP150, Stress-Test-Driven Qualification of and Failure Mechanisms Associated with Assembled Solid State Surface-Mount Components. JES

36、D226, RFBL Test Method for RF Biased Lifetesting 3 General requirements 3.1 Objective The objective of this procedure is to ensure that the power amplifier module to be qualified meets a generally accepted set of stress test driven qualification requirements. Qualification is aimed at components use

37、d in commercial or industrial operating environments. 3.2 Qualification family While this specification may be used to qualify an individual component, it is designed to also qualify a family of similar components utilizing the same fabrication process, design rules, and similar circuits. The family

38、 qualification may also be applied to a package family where the construction is the same and only the size and number of leads differs. Interactive effects of the semiconductor and package shall be considered in applying family designations. 3.3 Lot requirements Test samples shall comprise represen

39、tative samples from the qualification family. Manufacturing variability and its impact on reliability shall be assessed. Where applicable, the test samples will be composed of approximately equal numbers from at least three (3) nonconsecutive lots. Other appropriate means may be used to evaluate man

40、ufacturing variability. Sample size and pass/fail requirements are listed in Table 1 and Table 2. Table A and Table B give guidance on translating pass/fail requirements to larger sample sizes. JEDEC Standard No. 237 Page 3 3.3 Lot requirements (contd) ELFR requirements shall be assessed at a 60% co

41、nfidence level as shown in Table B. If a single unique and expensive component is to be qualified, a reduced sample size qualification may be performed using 1/3 the sample size listed in the qualification tables. 3.4 Production requirements All test samples shall be fabricated and assembled in the

42、same production site and with the same production process for which the device and qualification family will be manufactured in production. Samples need to be processed through the full production process including subcomponent testing, probe, handling, test, and any production screening operations.

43、 3.5 Reusability of test samples Devices that have been used for nondestructive qualification tests may be used to populate other qualification tests. Devices that have been used in destructive qualification tests may not be used in subsequent qualification stresses except for engineering analysis.

44、Non-destructive qualification tests are: Early Life Failure Rate, Electrical Parameters Assessment, External Visual, and Physical Dimensions. 3.6 Definition of electrical test failure after stressing Post-stress electrical failures are defined as those devices not meeting the individual device speci

45、fication or other criteria specific to the environmental stress. If the cause of failure is due to causes unrelated to the test conditions, the failure shall be discounted with a detailed explanation. All samples must be accounted for. 3.7 Required stress tests for qualification Table 1 and Table 2

46、list the qualification requirements for new products. Power supply voltage for biased reliability stresses should be at maximum voltage as defined in the device datasheet as the maximum specified power supply operating voltage, usually the maximum power supply voltage is 5% to 10% higher than the no

47、minal voltage. Some tests such as HTOL may allow for higher voltages to gain additional acceleration of stress time. JEP122 can provide guidance for accelerating common failure mechanisms. Table 2 lists the required stresses for a qualification family or category of change. Interactive effects from

48、the unchanged aspects of both the semiconductors and packaging must be assessed. 3.8 Pass/Fail criteria Passing all appropriate qualification tests specified in Table 1 and Table 2, either by performing the test, showing equivalent data with a larger sample size, or demonstrating acceptable generic

49、data (using an equivalent total percent defective at a 90% confidence limit for the total required lot and sample size), qualifies the device per this document. Generic data and larger sample sizes may be employed based upon a Chi Squared distribution using a total percent defective at a 90% confidence limit for the total required lot and sample size. Statistical definitions are defined in MIL-PRF 38535. (see www.dscc.dla.mil/Programs/MilSpec/). The minimum number of samples for a given defect level can be approximated by the formula: N = 0.5 2(2C+2, 0.1)