JEDEC JESD24-12-2004 Thermal Impedance Measurement for Insulated Gate Bipolar Transistors (Delta VCE(on) Method) ((This is an alternative method to JEDEC Standard No 24-6))《绝缘双极晶体管.pdf

1、JEDEC STANDARD Thermal Impedance Measurement for Insulated Gate Bipolar Transistors (Delta VCE(on)Method) JESD24-12 JUNE 2004 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Di

2、rectors level and subsequently reviewed and approved by the JEDEC legal counsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and ass

3、isting the purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. JEDEC standards and publications are adopted without regard to whether or not their adoption may

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5、 sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may be further processed and ultimately become an ANSI/EIA standard. No claims to be in

6、 conformance with this standard may be made unless all requirements stated in the standard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC at the address below, or call (703) 907-7559 or www.jedec.org Published

7、by JEDEC Solid State Technology Association 2004 2500 Wilson Boulevard Arlington, VA 22201-3834 This document may be downloaded free of charge; however JEDEC retains the copyright on this material. By downloading this file the individual agrees not to charge for or resell the resulting material. PRI

8、CE: Please refer to the current Catalog of JEDEC Engineering Standards and Publications online at http:/www.jedec.org/Catalog/catalog.cfm Printed in the U.S.A. All rights reserved PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by JEDEC and may not be reproduced without permission. Organi

9、zations may obtain permission to reproduce a limited number of copies through entering into a license agreement. For information, contact: JEDEC Solid State Technology Association 2500 Wilson Boulevard Arlington, Virginia 22201-3834 or call (703) 907-7559 JEDEC Standard No. 24-12 Page 1 THERMAL IMPE

10、DANCE MEASUREMENTS FOR INSULATED GATE BIPOLAR TRANSISTORS - (DELTA VCE(on)METHOD) (From JEDEC board Ballot JCB-04-38, formulated under the cognizance of the JC-25 Committee on Transistors.) 1 Scope The purpose of this test method is to measure the thermal impedance of the IGBT (Insulated Gate Bipola

11、r Transistor) under the specified conditions of applied voltage, current and pulse duration. The temperature sensitivity of the collector-emitter on voltage, VCE(on), is used as the junction temperature indicator. This is an alternative method to JEDEC Standard No. 24-6. 2 Terms and definitions The

12、following symbols and terms shall apply for the purpose of this test method: IM Emitter current applied during measurement of the collector-emitter ON voltage. IH Heating current through the collector or the emitter lead. VH Heating voltage between the collector and emitter. PH Magnitude of the heat

13、ing power pulse applied to the DUT in watts(W); the product of IHand VH. tH Heating time during which PHis applied. VCE(on) Voltage-temperature coefficient of VCE(on) with respect to TJ; in mV/C. K Thermal calibration factor equal to the reciprocal of VCE(on); in C/mV. TJ Junction temperature in deg

14、rees Celsius (C). TJI Junction temperature in degrees Celsius (C) before the start of the power pulse. TJF Junction temperature in degrees Celsius (C) after the end of the power pulse. JEDEC Standard No. 24-12 Page 2 2 Terms and definitions (contd) TXReference temperature in degrees Celsius (C). TXI

15、Reference temperature in degrees Celsius (C) before the start of the power pulse. TXFReference temperature in degrees Celsius (C) after the end of the power pulse. VCE(on) Collector-emitter voltage in millivolts (mV). VCE(on)iCollector-emitter voltage in millivolts (mV) before the start of the power

16、 pulse. VCE(on)fCollector-emitter voltage in millivolts (mV) after the end of the power pulse. VCE(M) Collector-emitter voltage during measurement periods. VCE Collector-emitter voltage during heating period. VGE Gate-emitter voltage used to drive the device during the heating period. tMD Measuremen

17、t delay time; is defined as the time from the removal of the heating pulse, PH, to the start of the VCE(on) measurement. tSW Sample window time during which the final VCE(on) measurement is made. ZJX Transient junction to reference point thermal impedance in degrees Celsius/watt(C/W). ZJXfor a speci

18、fied power pulse duration is: HXJIJFJXPT)T(TZ=where: TX= the change in reference point temperature during the heating pulse (for short heating pulses, such as at die attach evaluations, this term becomes negligible) RJXthe value referred to as steady state thermal resistance. This is the condition w

19、here the time of the heating pulses is sufficiently long that there is no change in the value of ZJX, or where (TJF TJI) TX does not change. JEDEC Standard No. 24-12 Page 3 3 Apparatus The apparatus for this test shall include the following: 3.1 A means for temperature measurements The preferred met

20、hod for measuring the case temperature is a thermocouple to measure a consistent reference location. The preferred reference location is on the case under the heat source, the IGBT die. The thermocouple wire should be AWG size 30; copper-constantan (type T) is preferred to optimize temperature readi

21、ng response. The junction thermocouple shall be welded, not soldered or twisted, to form a bead. Proper mounting of the thermocouple to ensure intimate contact to the reference is critical for system accuracy, which shall be 0.5 C. Alternative methods to measure the referenced case temperature can b

22、e used, such as IR thermal imaging, but these methods are usually less desirable economically. The method for temperature measurement is not relevant to this test method as long as the accuracy of the temperature measurement system is 0.5 C. 3.2 A setup for VCE(on) or K-factor calibration A VCE(on)

23、or K-factor calibration shall be determined using a controlled environment. A recirculating bath or an oven that is capable of holding the case temperature during the device calibration to within 1 C over a 25 C to 125 C range, the possible temperature range for measuring the K-factor, can be used.

24、A circuit, such as Figure 1, shall be used to make the measurement to determine this K-factor. The current source used to generate IMshall have an accuracy to 2% . The meter used to measure VCE(on)shall be capable of 1 mV resolution. The VGEsupply shall have an accuracy to 2%. The wires used to supp

25、ly the device to current source connections shall be sufficient to handle the measurement current (AWG 22 is sufficient to carry up to 100 mA). A typical VCE(on) vs. Temperature curve will be similar to Figure 2. Figure 1 Simplified schematic for Rthjc measurement VCE IME C GVGEDUTJEDEC Standard No.

26、 24-12 Page 4 3 Apparatus (contd) 3.3 A setup for thermal testing Testing can be implemented using a circuit that allows the control of the test current, IH, and the measurement current, IM, through the use of a high speed switching circuit. This circuit should effectively measure the VCE(on)at IMdu

27、ring the pre-power application phase of the test. The measurement will be held for later comparison to the post power measurement. Then the circuit will switch to the high current mode and will set up the switches that control IHand VHduring the heating phase of the thermal testing. After the heatin

28、g pulse is complete the circuit should effectively measure the VCE(on)at IM as done during the pre-power application. 4 Measurement of the temperature sensitive parameter 4.1 VCE(on) versus temperature calibration The required calibration of VCE(on)vs. TJ, or VCE(on), is accomplished by monitoring V

29、CE(on) and IMas the heat sink temperature (and thus the DUT temperature) is varied by external heating. VGEshall be set at a condition that results in the DUT being full on. IMmust be chosen so that there is no significant self-heating but provides sufficient temperature sensitivity. This will be de

30、pendent upon the DUT power dissipation, or the DUT die size (IMcould be 1 mA or less for smaller devices and upward of 100 mA for larger devices). It is prudent engineering practice to generate this curve with more then 3 points. A typical calibration curve usually has a linear relation over a 25 C

31、to 125 C range, such as Figure 2. Figure 2 Example of a calibration curve TJ(C) VCE(mV) 500 200 25 IM125 JEDEC Standard No. 24-12 Page 5 4 Measurement of the temperature sensitive parameter (contd) 4.1 VCE(on) versus temperature calibration (contd) A suitable sample-and-hold voltmeter or oscilloscop

32、e shall be used to measure the collector-emitter voltage at selected temperatures. VCE(on)shall be measured within 1 mV, or within 2% of VCE(on), which ever is less. 4.2 K-factor A calibration factor, K (which is the reciprocal of the slope of the curve on Figure 2) can be defined as: C/mV V - VT -

33、T= KCECEJJ1212It has been observed experimentally that the VCE(on)or K-factor variation for devices within a given device type class is small. This should be verified. Usually a 10 to 12 piece sample from a device lot can be measured. The average, KAV, and standard deviation (K), of the K-factor is

34、determined. If Kis less than or equal to 3% of KAV, then KAVcan be used. If Kis greater than 3% of KAV, then all the devices in the lot need to be measured for their respective K-factor and the individual values for the VCE(on)shall be used for the calculations of thermal resistance or thermal respo

35、nse. As an alternative to using individual values of K, the manufacture may establish internal limits unique to their product that ensures atypical product removal from the population (lot-to-lot and within-the-lot). The manufacturer shall use statistical techniques to establish the limits. 5 Test p

36、rocedure 5.1 Calibration K-factor determination shall be done per 4, being mindful of the constraints in 4.2. 5.2 Reference temperature point The reference temperature point location must be specified and the temperature shall be monitored using the requirements of 3.1. The reference point is usuall

37、y chosen to be on the bottom of the transistor case directly below the IGBT die. Alternatively, this reference point should be as close to the thermal path generated by the die into the case (or the heat sink location that is accessible) as practicable, so it reflects the effects of mounting the DUT

38、 in a real application. JEDEC Standard No. 24-12 Page 6 5 Test procedure (contd) 5.2 Reference temperature point (contd) If it is determined that the temperature TXincreases more than 5 % of the measured junction temperature rise during the power pulse, then one of following options must be taken. T

39、he heating pulse magnitude must be decreased. Or the DUT must be mounted to a temperature controlled heat sink and temperatures must be measured properly to assure the TXrequirement. Or the calculated value of thermal impedance must be corrected to take into account the thermal impedance of the refe

40、rence point to the cooling medium (i.e., the heat sink). Temperature measurements for monitoring, controlling and/or correcting for reference point temperature changes are not required if the tH is short enough to ensure that the heat generated by the DUT has not had time to propagate through the pa

41、ckage. In this case typical values for tHare 10 ms to 100 ms dependent upon the package design and materials. 5.3 Steady state thermal resistance, RJXPrior to the power pulse: a) Establish the reference point temperature TXI. b) Apply the gate voltage, VGE, needed to assure full conduction. c) Measu

42、re the initial VCE(on)iat the specifiedIM.Apply the power pulse a) Verify VH, observe that there are no anomalies with the pulse. b) Verify IH, observe that there are no anomalies with the pulse. c) Verify that tHis great enough that the device is in a steady state condition. d) Measure the TXFat th

43、e end of the power pulse. Post Power Pulse a) Apply the gate voltage, VGE, needed to assure full conduction. b) Measure the VCE(on)f at the specified IM.c) Establish the delay time,tMD. This can be used to extrapolate the actual TJFof the post power pulse. JEDEC Standard No. 24-12 Page 7 5 Test proc

44、edure (contd) 5.4 Thermal response, ZJXPrior to the power pulse: a) Establish the reference point temperature TXI. b) Apply the gate voltage, VGE, needed to assure full conduction. c) Measure the initial VCE(on)iat the specifiedIM.Apply the power pulse a) Verify VH, observe that there are no anomali

45、es with the pulse. b) Verify IH, observe that there are no anomalies with the pulse. c) Verify that tHis short enough that the device is not exceeding the conditions of paragraph 5.2 for a non-heat-sunk device. This can be done by measuring the TXFat the end of the power pulse. Post Power Pulse a) A

46、pply the gate voltage, VGE, needed to assure full conduction. b) Measure the VCE(on)f at the specified IM.c) Establish the delay time,tMD. This can be used to extrapolate the actual TJFof the post power pulse. 5.5 Calculate thermal resistance, RJX, or thermal impedance, ZJXa) The value of thermal re

47、sistance is calculated per the formula below: RJX= TJ / PHTX / PH = ( VCE(on)f - VCE(on)I / VCE(on)/ PH TX / PH C/W b) The value of thermal response is calculated per the formula below: ZJX= TJ / PH = ( VCE(on)f - VCE(on)I / VCE(on)/ PHC/W because the term TX / PH approaches 0 if the conditions for

48、thermal response are met.NOTE There are several semi-automated systems available today, because of the advances made in computer controlled testing systems, that can do much of the data taking and calculations for the procedures outlined in this section. JEDEC Standard No. 24-12 Page 8 6 Test condit

49、ions and measurements Typical waveforms are below where VCE1 = VCE(on)i VCE2 = VCE(on)fDT = Delay time = tMDPT = PH tSW = the sampling window, (10 s) this value is not always fixed NOTE 1 Some test equipment may provide a VCEdirectly instead of VCE(on)iand VCE(on)f; this is an acceptable alternative. Record the value of VCE. NOTE 2 Some test equipment may provide ZJXdirectly instead of VCE(on)iand VCE(on)ffor thermal resistance calculations; this is an acceptable alternative