JEDEC JESD24-1985 Power MOSFET-s《MOSFET功率》.pdf

1、b - - - - EIA JESD24 85 I 3234b00 0005508 b I .- . I I JEDEC STANDARD POWER MOSFETs No. 24 JEDEC Solid State Products Engineering Council ,EIA x JESD24 85 m 3234600 0005509 8 m NOTICE This JEDEC Standard or Publication contains material that has been prepared, progressively reviewed, and approved th

2、rough the JEDEC Council level and subsequently reviewed and approved by the EIA General Counsel. JEDEC Standards and Publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of p

3、roducts, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for his particular need: Existence of such standards shall not in any respect preclude any member or nonmember of JEDEC from manufacturing or selling products not conforming to such standards, nor s

4、hall the existence of such standards preclude their voluntary use by those other than IA members whether the standard is to be used either domestically or internationally. Recommended Standards are adopted by JEDEC without regard to whether or not their adoption may involve patents or articles, mate

5、rials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC Standards or Publicat ions. The information included in JEDEC Standards and Publications represents a sound approach to product specif

6、ication and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC Standard or Publication. may be further processed and ultimately become an EIA Standard. Inquiries, comments, and suggestions relative to ,the c

7、ontent of this JEDEC Standard or Publication should be addressed to the JEDEC Executive Secretary at EIA Headquarters, 2001 Eye Street, N.W., Washington, D.C. 20006. PRICE : $18.00 Published by ELECTRONIC INDUSTRIES ASSOCIATION Engineering Department 2001 Eye Street, N.W. Washington, D.C. 20006 Copy

8、right 1985 ELECTRONIC INDUSTRIES ASSOCIATION Printed in U.S.A. f -7 i - EIA JESD24 85 E 3234600 0005518 9 E , JEDEC Standard No, 24 10 DC VALUE, COMPONENT NO ALTERNATING- NO ALTERNATINQ, CWPONENT Id Idm R WTMEANSQUAFI E MAXIMUM (PEAK) VALUE OF VALUE OF 1 I ING ti I r I i I iD INSTANTANEOUS n PEAK) I

9、 - I LA WITH ALTERNATING -1 COMPONENT Figure B. Use of Letter Symbols (applies to any volta or curnnt temis). Symbol - Term Ia gate current, dc IaF forward gate current JaR reverse gate current IGSS rtverse gate current, dfain shorf-circuited to source lass F forward gate current, to source drain sh

10、ort-circuited IQSS R reverse gate current, drain short-circuited to source IS source current, dc Definition The direct current into the gate terminal. The direct current into the gate terminal with a forward gatemsource voltage applied. The direct current into the gate terminal with a reverst gate-s

11、ource voltage applied. The direct current into the gate terminal of a junction-gate field-effect transistor when the gate terminai is reverse biased with respect to the source terminal and the drain terminal is short- circuited to source terminai. The direct current into the gate terminal of an insu

12、lated. gate 6eld.effect transistor with a forward gate-source voltage applied and the drain terminal short-circuited to the source terminal. The direct current into the gate terminal of an insulated- gate field-effect transistor with ? reverse gate-source voltage applied and the drain terminal short

13、-circuited to the source terminal. The direct current into the (ource terminal, 6 EIA JESD24 85 3234600 0005519 O M JEDEC Standard No. 24 Symbol %uxl source cutoff cumnt DcBnition The direct current into the source terminal of a depletion= type transistor with a specified gateadrain voltage applied

14、to bias the device to the off-state. IS DS gero-gat e-voltage source current The direct current into the source terminal when the gate- drain voltage is zero. Note: This an an on-state current in a depletion-type device, an offYstate current in an enhancement4ype device. PT PT total nonreactive powe

15、r input to all terminals The sum of the products of the dc input currents and volt ages. The sum of the products of the instantaneous input currents and voltages. nonreactive power input, instantaneous total, to ali terminals The sma-signal resistance between drain and source terminals with a specif

16、ied gate-source voltage applied to bias the device to the on-state. small-signal drain- source on=state resistance rde(on) Nots: For a depletion-type device, the gate-source voltage may be zero. static drain-source on-state resistance The dc resistance between the drain source terminals with a speci

17、6ied gate-source voltage applied to bias the device to the on-state. Note: For a depletion-type device, the gate-source voltage mw be zero. (Refer to thermal resistance definition in Section 1.2). RB RdUA thermal resistance thermal resistance, case-to-ambient The thermal resistance (steady state) fi

18、om the device case to the ambient, . The sum of voltage turn-off delay time and voltage rise time, i.e., td(off)u + trua voltage tiirn90ff time turn-on time Synonym for current turn-on time (see Note 1). ton ton() current turn-on time The sum of current turn-on delay time and current rise time, i.e.

19、, td(on)i + tri. voltage turn-on time The sum of voltage turn-on delay time and voltage fall time, i.e., t,qonju + tiu. pulse duration . (formerly pulse time) The time interval between a reference point on the leading edge of a pulse waveform and a reference point on the trailing edge of the same wa

20、veform. Note: The two reference points are usually 90% of the steady-state amplitude existing before the leading edge. If the reference points are 50% points, the symbol t, and term average pulse duration should be used, Synonym for current rise time (see Note 1). tr tri rise time current rise time

21、The time interval during which the drain current changes from 10% to 90% of its peak on-state value, ignoring spikes that are not charge-carrier-induced. voltage rise time The time interval during which the drain voltage changes from 10% to 90% of its peak off-state value, ignoring spikes that are n

22、ot charge-carrier-induced. tti . current tail time The time interval following current fall time during which the drain current changes from 10% to 2% of its peak on- state value, ignoring spikes that are not charge=carrier- induced. The time interval between a reference point on the leading edge of

23、 a puIse waveform and a reference point on the trailing edge of the same waveform, with both reference points being 50% of the steadystate amplitude of the waveform existing after the leading edge, measured with respect to the steady-state amplitude existing before the leading edge. average puise du

24、ration (formerly pulse average time) j EIA JESD24 85 m 3234600 0005522 O m JEDEC Standard No. 24 Symbol Definition Note: If the reference points are not 50% points, the symbol t, and term pulse duration should be used. turn-off crossover time, (This ia a reserve symbol to be used if nee of to wiii c

25、ause eonusion.) For definition, see to. Note 1: As names of time intervals for characterizing transistors, the tem “fall time“ and %se time“ always refer to the change that is taking place in the magnitude of the output current even though measurements may be made using voltage waveforms. In a pure

26、where n is an integral number. O (4) Power: Rounded 13 series Case temperatures are selected from item 2.3.3. 2.3.3 Standard Values for Characterietics (1) Specified limits: Rounded 13 series* (2) Test Voltages and ): two standard (3) Power, continuous (PT): steps. (a) for 5 160 W: two standard step

27、s (b) for 160 W: one standard step (4) Temperature, operating junction (Tj), and stor- age (Tatg): two standard steps. 2,4.3 Minimum Differences for Characteristics (1) Transconductance (gfe): (EIA JESD24 85 3234600 0005530 T - = I JEDEC Standard No. 24 (a) for increase or decrease of both upper and

28、 lower limits: one standard step (3) Drain-sore redsface rDS(on): two sfandd steps. (b) for change in only lower limit: two standard steps, (change in upper limit alone is not a cri- (4) Drain cut-off cuirent (Ims for MOSFET, (,t,) for JFET): two orders of magnitude. tetis). (6) Threshold voltage b(

29、:b): two standd steps (2) Input capacitance (Cia), Reverse transfer cam and output capacitance (Goa): pacitance (a) as ,above, under item 1 two standard steps. (a) as above, under item 1 (b) for change in only upper limit: two standard steps (change lower limit alone is not a crite- ria). (b) for ch

30、ange in only upper limit: two standard steps (change in lower limit alone is not a crite- ria). EIA JESDZ4 85 U 3234b00 0005533 3 U JEDEC Standard No. 24 CHAPTER 3 ELECTRIc1AL VERIFICATION TESTS 3.1 INTRODUCTION All measurements should be made at thermal equilib- rium. A condition of thermal equilib

31、rium is achieved il halving the time between application of power and measurement causes no change in the result within the required accuracy. Unless specified otherwise, the transistor case temperature should be maintained at approximately 25OC by use of an appropriate heat sink, when necessary. Th

32、e connecting lines shown in the circuit diagrams have negligible resistance compared to their lowest terminating impedance. Shown are resistors, induc- tors, and capacitors having an ideal characteristic at the used frequency range. The battery symbol indi= cates voltage sources having zero impedanc

33、e, which in practice requires use of generous bypassing, and current sources approximate an infinite resistance. In practice, power supplies having current limiting should be used for voltage sources. All voltmeters and scopes have infinite input resistance and all ammeters have zero resistance, unl

34、ess otherwise noted; a practical ap- proximation to these ideals is achieved if doubling or halving does not produce a change in the measured values that exceeds the accuracy of the test. All cir- cuit values are nominal and should be achieved within limita of a few percent or as dictated by equipme

35、nt capabilities consistent with good engineering practice. The listing of the following tests does not imply that all must be performed by either the manufacturer or the user; It is the responsibility of the user and man- ufacturer to agree to any series of specific tests or test conditions, and the

36、 further responsibility of the user to establish meaningful relationships between these tests and the performance of the power MOSFET in a particular application. Except when no$ applicable, the MOSFET connec. tions are shown for a dc“ technique; the same gen- eral configuration applies when a pulse

37、 technique or a curve tracer is used to perform the test. An a-channel enhamement type transistor is shown as the transistor under test in the test circuits. These test methods wil also apply to p-channel devices by appropriate polarity changes in the test circuit ele- As many power MOSFETs have cut

38、-off frequencies on * ments. the order of a gigahertz, parasitic oscillations may be troublesome unless certain precautions are observed. Usually oscillations are .prevented by observing the following guidelines: (1) Keep lead and trace lengths short. (2) Place ferrite beads on the gate lead close t

39、o the gate terminal or use a resistor of 100 to 1000 Q in series with the gate. (3) Avoid a lwout which may couple output signal to the input. (4) Surround the MOSFET with a ground plane and shield output from input. (5) Use noninductive resistors. Except where specifically noted, the tests apply wh

40、eth- er or not gate protection elements are included in the MOSFET. Protection elements are shown as zener diodes, although they need not necessarily be of this type, Depletion-mode transistors are not specically covered in the material which follows. 3.2 MAXIIMUM RATINGS 3.2.1 Introduction, This se

41、ction describes tests which are intended to ver- ify the maximum ratings given in transistor registra- tion formats; they are not tests used for developing the maximumratings nor are they intended for estab- lishing performance or quality levels. 3.2.2 Veacation Criteria To verify a given maximum ra

42、ting for a transistor, the transistor shall be tested as described in the ap- plicable subsection, The transistor shallbe capable of meeting all the electrical characteristics of the reg. istration at the conclusion of the test procedure, after the transistor has been allowed to reach thermal equi.

43、librium at 25OC or other specified temperature. 3.2.3 Storage Temperature, Minimum 3.2.3.1 Test Conditions (1) Storage temperature at;ated Ttg (min.) (2) Test duration of six (6) hours at the rated T, ( Temperature: Ta (il Ta # 26OC) 3.3.3.2 Test Circuits (b) Drain Current: ID (2) Drain-Source Break

44、down Voltage - V(BR)DSX* See circuit B. (a) Case Temperature: Tc (id Tc # 25C) (b) Gate Supply Voltage: VGU (e) Gate Resistance: RQ (d) Drain C-nt: ir, (3) Gate-Source Breakdown Voltage - V(BR ass. See circuit C (for gate protected parts only (a) Uase Temprature: TC (il To # 26OC) (b) Gate Currenf:

45、la Continuous e Circuit A 3.3.2.4 Procedure (1) V(BR)DSS The drain supply VOO is increased to achieve the required drain current, After a stable level ia achieved, the drain-source voltage is measured. (BRJDSX The gate supply voltage Vea, is applied first. The drain supply VDD is then increased to a

46、chieve the required drain current. Alfer a stable level is achieved, the drain=source voltage is measured. (3) V(BR)QSS The gat C.T. or P (circuit B) e EIA JESD24 85 m 3234600 0005537 2 m 3.3.3.4 Procedure The supply, Vas, is increased from zero nntii the spec. i6ied gate voltage is achieved. ID ia

47、then meawntj. 3.3.4 Static Drain-Source On-State Resistance - VDS(on) 3.3.4.1 Description This parameter specifies the devices resistonce beg tween Drain and Source with the Gate at a specie fied forward=bias voltage. Cate voltage muat be enough so that changes h VDS are roughly prQcrporn tional to

48、changes in ID. 3.3.4.2 Test Circuit r-l POWLR SUPPLY Curve nacer (C.T.) or Pulse (P) Circuit B 3.3.4.3 Test Conditions to be Specified (1) Case Temperature: TC (if Tc # 26OC) JEDEC Standard No. 24 (2) Gate Source Voltage: V C.T. or P (circuit B) 3.3.4.4 Procedure VDS i9 measured and PDS(,) is calcul

49、ated a9 VDS fD. 3.3.6 Gate-Source Threshold Voltage - Vs(tr) 3,&$.1 Description The threshold voltage specification defines a range of forward gate voltage for an enhancement type transis- tor at a drain current slightly above the cut-off level, 1s. The threshold voltage is considered a bound- iiry between the offastate and on-state. 3.3.6.2 Test Circuit - Continuous dc circuit A I SHE WAVE OR PULSED POWER SUPPLY . v66 Curve Zacer (C.T.) or Pdse (P) circuit B