JEDEC JESD245-2015 Byte Addressable Energy Backed Interface.pdf

1、JEDEC STANDARD Byte Addressable Energy Backed Interface JESD245 DECEMBER 2015 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors level and subsequently reviewed and appr

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9、lington, VA 22201-2107 or refer to www.jedec.org under Standards-Documents/Copyright Information. JEDEC Standard No. 245 -i- BYTE ADDRESSABLE ENERGY BACKED INTERFACE Contents PageForeword iiIntroduction ii1 Scope 12 Normative references 13 Terms and definitions 14 NVDIMM overview 55 I2C 66 Serial Pr

10、esence Detect 127 Features 138 Register Map 229 Host Operation Workflows 94Figures 1 NVDIMM overview 52 Legend for I2C operations 63 I2C Read Byte 74 I2C Write Byte 75 I2C Block Read 76 I2C Block Write 87 I2C paging mechanism 10Tables 1 Required SPD fields 122 Firmware image header 193 Temperature v

11、alue bit definition 214 Page 0 categories 225 Page 0 register map 236 Page 1 categories 637 Page 1 register map 638 Page 2 categories 719 Page 2 register map 7110 Page 3 categories 8111 Page 3 register map 81JEDEC Standard No. 245 -ii- Foreword This standard has been prepared by JEDEC. The purpose o

12、f this standard is definition of an energy backed byte addressable function on a nonvolatile dual in-line memory module (NVDIMM). This standard defines the feature set and commands implemented by the energy backed byte addressable function on the NVDIMM. Introduction NVDIMM is a DDRbased memory modu

13、le that can be integrated into a standard platform. An Energy Backed Byte Addressable Function on a NVDIMM is designed to preserve data in the event of the power failure. An Energy Backed Byte Address Function is backed by a combination of SDRAM and non-volatile memory (e.g., NAND flash) on the NVDI

14、MM. It operates at DDR speeds and can provide persistent storage by backing up the SDRAM contents into the non-volatile memory in the event of a power failure. This is made possible by an Energy Source (e.g., super-capacitor) which maintains charge on the module enabling back-up of data from SDRAM t

15、o the non-volatile memory, providing a storage-class memory solution. To be able to provide interoperability and the ability for platform and platform software (e.g., BIOS) to support NVDIMMs from various manufacturers, standardization of the host to module interface, discovery mechanism, the featur

16、e set and command operations are required, as described in this document. JEDEC Standard No. 245 Page 1 BYTE ADDRESSABLE ENERGY BACKED INTERFACE (From JEDEC Board Ballot JCB-15-44, formulated under the cognizance of the JC-45.6 Subcommittee on Hybrid Modules.) 1 Scope This standard specifies the hos

17、t and device interface for a DDR4 DIMM interface module that achieves non-volatility by copying SDRAM contents into non-volatile memory when Host power is lost using an Energy Source managed by either the module or the Host. Although this standard is targeted towards DDR4 NVDIMM only, it does not pr

18、eclude adoption of this standard by other implementations (e.g., DDR3 NVDIMM). 2 Normative References The following normative documents contain provisions that, through reference in this text, constitute provisions of this standard. For dated references, subsequent amendments to, or revisions of, an

19、y of these publications do not apply. However, parties to agreements based on this standard are encouraged to investigate the possibility of applying the most recent editions of the normative documents indicated below. For undated references, the latest edition of the normative document referred to

20、applies. DDR4 SPD Contents NVDIMM Revision 0.5 EE1004 and TSE2004 Device Specification SPD4_01_06 I2C Bus Specification Revision 4 System Management Bus (SMBus) Specification Version 2.0 3 Terms and definitions For the purposes of this standard, the terms and definitions given in the document includ

21、ed in clause 2 “Normative References” and the following apply: 3.1 Acronyms DDR3 Double Data Rate version 3 DDR4 Double Data Rate version 4 NVM Non-Volatile Memory DIMM Dual In-line Memory Module NVDIMM Non-volatile Dual In-line Memory Module SPD Serial Presence Detect I2C Inter-IC ES Energy SourceS

22、DRAM Synchronous Dynamic Random Access Memory JEDEC Standard No. 245 Page 2 3.2 Terms and definition Abort: Operation that stops the currently running operation on the module. See 7.1.9 for more information. Arm: Operation that enables or disables trigger(s) for a Catastrophic Save operation. See 7.

23、1.4 for more information. Catastrophic Save: Process of copying the SDRAM contents into non-volatile memory when power is lost. The Catastrophic Save operation is initiated when an enabled trigger occurs or a write to an I2C register. See 7.1.1 for more information. Device Managed Policy: Energy Sou

24、rce policy where the module manages the Energy Source used during the Catastrophic Save operation. Energy Source: A device that is capable of storing and providing energy to the module during a Catastrophic Save operation. Erase: Operation that deletes the previously saved SDRAM content in non-volat

25、ile memory. See 7.1.3 for more information. Factory Default: Operation that erases all non-volatile memory on the module and resets readable registers to its factory default value except the data needed to determine warranty compliance. This operation does not impact firmware on the module. See 7.1.

26、10 for more information. Firmware Operations: Operations that are related to updating the firmware on the module. See 7.1.8 for more details. Host: The system in which the module is installed in. Host Managed Policy: Energy Source policy where the Host manages the Energy Source used during the Catas

27、trophic Save operation. I2C Bus: A bidirectional 2-wire bus for efficient inter-IC control. Management Operations: Operations that either reset the controller on the module or clear status register(s). See 7.1.5 for more details. Restore: Process of restoring previously saved SDRAM contents from non

28、-volatile memory to SDRAM. See 7.1.2 for more information. Self-refresh: The SDRAM state that maintains data integrity without requiring any host interaction. SDRAM Mode Registers: The registers on SDRAM that configures the SDRAM for operational use. Some of the mode registers are write-only registe

29、rs. Set Energy Source Policy: Operation that configures the Energy Source to be used by the module in the Catastrophic Save operation. See 7.1.6 for more details. JEDEC Standard No. 245 Page 3 3.2 Terms and definition (contd) Set Event Notification: Operation that either enables or disables notifica

30、tion support on the module when certain event occurs. See 7.1.7 for more details. Typed Block Data: A collection of data that is transferred between the Host and module in 32 bytes increment. Vendor Log Page: An optional area on the module that is accessible by the Host and containing vendor specifi

31、c data useful to triage issues on the module. See 7.10 for more details. 3.3 Keywords Several keywords are used to differentiate levels of requirements and options, as follow: Can - A keyword used for statements of possibility and capability, whether material, physical, or causal (can equals is able

32、 to). Expected - A keyword used to describe the behavior of the hardware or software in the design models assumed by this standard. Other hardware and software design models may also be implemented. Ignored - A keyword that describes bits, bytes, quadlets, or fields whose values are not checked by t

33、he recipient. Mandatory - A keyword that indicates items required to be implemented as defined by this standard. May - A keyword that indicates a course of action permissible within the limits of the standard (may equals is permitted). Must - The use of the word must is deprecated and shall not be u

34、sed when stating mandatory requirements; must is used only to describe unavoidable situations. Optional - A keyword that describes features which are not required to be implemented by this standard. However, if any optional feature defined by the standard is implemented, it shall be implemented as d

35、efined by the standard. Reserved - A keyword used to describe objectsbits, bytes, and fieldsor the code values assigned to these objects in cases where either the object or the code value is set aside for future standardization. Usage and interpretation may be specified by future extensions to this

36、or other standards. A reserved object shall be zeroed or, upon development of a future standard, set to a value specified by such a standard. The recipient of a reserved object shall not check its value. The recipient of a defined object shall check its value and reject reserved code values. Shall -

37、 A keyword that indicates a mandatory requirement strictly to be followed in order to conform to the standard and from which no deviation is permitted (shall equals is required to). Designers are required to implement all such mandatory requirements to assure interoperability with other products con

38、forming to this standard. JEDEC Standard No. 245 Page 4 3.3 Keywords (contd) Should - A keyword used to indicate that among several possibilities one is recommended as particularly suitable, without mentioning or excluding others; or that a certain course of action is preferred but not necessarily r

39、equired; or that (in the negative form) a certain course of action is deprecated but not prohibited (should equals is recommended that). Will - The use of the word will is deprecated and shall not be used when stating mandatory requirements; will is only used in statements of fact. 3.4 Conventions T

40、his standard uses the following conventions: A binary number is represented in this standard by any sequence of digits consisting of only the Western-Arabic numerals 0 and 1 immediately followed by a lower-case b (e.g., 0101b). Spaces may be included in binary number representations to increase read

41、ability or delineate field boundaries (e.g., 0 0101 1010b). A hexadecimal number is represented in this standard by any sequence of digits consisting of only the Western-Arabic numerals 0 through 9 and/or the upper-case English letters A through F immediately followed by a lower-case h (e.g., FA23h)

42、. Spaces may be included in hexadecimal number representations to increase readability or delineate field boundaries (e.g., B FD8C FA23h). A decimal number is represented in this standard by any sequence of digits consisting of only the Western-Arabic numerals 0 through 9 not immediately followed by

43、 a lower-case b or lower-case h (e.g., 25). A range of numeric values is represented in this standard in the form “a to z“, where a is the first value included in the range, all values between a and z are included in the range, and z is the last value included in the range (e.g., the representation

44、“0h to 3h“ includes the values 0h, 1h, 2h, and 3h). When the value of the bit or field is not relevant, x or xx appears in place of a specific value. JEDEC Standard No. 245 Page 5 4 NVDIMM overview For modules containing both SDRAM and non-volatile memory, a non-volatile DIMM (NVDIMM) can be created

45、 if the contents of the SDRAM can be persisted to the non-volatile memory when power is lost using an alternative power source and the contents of the SDRAM restored when power is available. This type of NVDIMM is classified as one that supports the Byte Addressable Energy Backed Interface. This sta

46、ndard defines the host and device interface for a DDR4 DIMM interface module that implements the Byte Addressable Energy Backed Interface. The module achieves non-volatility by copying SDRAM contents into non-volatile memory when Host power is lost using an Energy Source managed by either the module

47、 or the Host. The Byte Addressable Energy Backed Interface is controlled by the Host through a set of I2C registers using the standard I2C Bus implemented through the SCL and SDA pins on the DDR4 bus. Centralized Energy Source power is provided through the 12 V pin on the DDR4 bus. Energy Source (Op

48、tional)ControllerSDRAMHost(Motherboard)I2C MasterThis Specification288-pin DIMMNVDIMMNon-Volatile MemoryEnergy SourceControlSAVE_nOptional External TriggerEVENT#12VHost Energy Source(Optional)Figure 1 NVDIMM overview JEDEC Standard No. 245 Page 6 5 I2C This section describes the I2C support a module

49、 compliant with this standard shall support. 5.1 I2C bus For I2C bus frequency up to 100 kHz, modules I2C bus support shall be compliant with SMBus 2.0. Modules shall also support I2C Fast-mode (up to 400 kHz) and Fast-mode Plus (up to 1 MHz) (see I2C Bus specification for more details). Modules shall not clock stretch any I2C operations. A module supporting the Byte Addressable Energy Backed Interface shall implement an I2C slave with the I2C address of 1000YYYx where YYY can range from 0-7 and x indicates a read or write operation. 5.2 I2C operations Modules shall support the I2C r