JEDEC JESD245B 01-2017 Byte Addressable Energy Backed Interface.pdf

1、 JEDEC STANDARD Byte Addressable Energy Backed Interface JESD245B.01 (Revision of JESD245B, July 2017) SEPTEMBER 2017 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors

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9、103 North 10th Street Suite 240 South Arlington, VA 22201-2107 or refer to www.jedec.org under Standards-Documents/Copyright Information. JEDEC Standard No. 245B.01 -i- BYTE ADDRESSABLE ENERGY BACKED INTERFACE (From JEDEC Board Ballot JCB-17-15, formulated under the cognizance of the JC-45.6 Subcomm

10、ittee on Hybrid Modules.) CONTENTS Foreword v Introduction . v 1 Scope 1 2 Normative References 1 3 Terms and definitions 2 3.1 Acronyms 2 3.2 Terms and Definitions . 3 3.3 Keywords . 4 3.4 Conventions . 5 4 Introduction 6 5 I2C 7 5.1 I2C Bus . 7 5.2 I2C transactions 7 5.3 Paging 10 5.4 Typed Block

11、Data 11 6 Serial Presence Detect 12 6.1 Byte Addressable Energy Backed Interface Discovery . 12 7 Features . 13 7.1 Controller Ready 13 7.2 Operations 13 7.2.1 Catastrophic Save operation . 13 7.2.2 Restore operation 15 7.2.3 Erase operation . 16 7.2.4 Arm operation . 16 7.2.5 Management operations

12、17 7.2.6 Set Energy Source Policy operation . 17 7.2.7 Set Event Notification operation . 17 7.2.8 Firmware operations . 18 7.2.9 Factory Default operation . 19 7.2.10 Reset Controller operation 20 7.2.11 Operational Unit operations 21 7.2.12 Atomic Arm and Erase operation . 21 7.2.13 Abort operatio

13、n . 22 7.3 Energy Source 23 7.3.1 Local Energy Source. 23 7.3.2 Tethered Energy Source . 23 7.3.3 Host Energy Source 23 7.3.4 Shared Energy Source . 23 7.3.5 Energy Source Policy . 24 7.4 Event Notification 24 JEDEC Standard No. 245B.01 -ii- 7.5 Error and Warning Thresholds 25 7.6 Module Firmware 25

14、 7.7 CRC Algorithm 28 7.8 Error Injection 29 7.9 Statistics . 29 7.10 Thermal 30 7.11 Host Area . 31 7.12 Vendor Log Page . 31 7.13 Vendor-Specific . 31 7.14 LCOM Interface 31 7.15 Label Data . 32 7.16 Catastrophic Save transition registers 32 8 Register Map 33 8.1 Page 0 register map 33 8.1.1 Pagin

15、g Mechanism registers . 36 8.1.2 Version registers . 37 8.1.3 Characteristics registers 39 8.1.4 Runtime Command registers 49 8.1.5 Runtime Command Status registers 54 8.1.6 Catastrophic Save registers . 62 8.1.7 Thresholds registers 64 8.1.8 Module registers . 67 8.1.9 NVM Subsystem registers 74 8.

16、2 Page 1 register map 75 8.2.1 Paging Mechanism registers . 76 8.2.2 Energy Source Version registers . 76 8.2.3 Energy Source Characteristics registers 77 8.2.4 Energy Source Runtime Command registers 79 8.2.5 Energy Source Runtime Command Status registers . 80 8.2.6 Energy Source registers 80 8.3 P

17、age 2 register map 81 8.3.1 Paging Mechanism registers . 83 8.3.2 Device Statistics registers . 83 8.3.3 Error Injection registers 92 8.3.4 Host Area registers . 96 8.4 Page 3 register map 98 8.4.1 Paging Mechanism registers . 99 8.4.2 Typed Block Data registers 100 8.4.3 Firmware Update registers 1

18、03 8.4.4 Byte and Word Transaction Data registers for Typed Block Data . 103 8.4.5 Block Transaction Data registers for Typed Blocked Data 108 8.5 Page 4 register map 109 8.5.1 OPEN_PAGE Offset 0x00. 109 8.5.2 PDA_SUPPORTED Offset 0x04 . 109 8.5.3 PDA_VALID Offset 0x05 . 109 8.5.4 MRx_SHARED registe

19、rs Offsets 0x10-0x11 to 0x1C-0x1D 110 8.6 Page 5 register map 110 JEDEC Standard No. 245B.01 -iii- 8.6.1 OPEN_PAGE Offset 0x00 111 8.6.2 MRx_PDA_SDRAMyy registers Offsets 0x10-0x11 to 0xFE-0xFF 111 8.7 Page 6 register map 111 8.7.1 OPEN_PAGE Offset 0x00. 111 8.7.2 RCD_FUNCTIONS_SUPPORTED0 Offset 0x0

20、4 111 8.7.3 RCD_FUNCTIONS_SUPPORTED1 Offset 0x05 112 8.7.4 RCD_FUNCTIONS_VALID0 Offset 0x06 112 8.7.5 RCD_FUNCTIONS_VALID1 Offset 0x07 112 8.7.6 Control word registers 112 8.8 Page 7 register map 113 8.8.1 OPEN_PAGE Offset 0x00. 113 8.8.2 Control word registers 113 8.9 Page 8 register map 113 8.9.1

21、OPEN_PAGE Offset 0x00. 113 8.9.2 Control word registers 113 8.10 Page 9 register map 114 8.10.1 OPEN_PAGE Offset 0x00. 114 8.10.2 Control word registers 114 9 Host Operation Workflows . 115 9.1 Controller Ready workflow . 115 9.2 Catastrophic Save workflow 115 9.3 Restore workflow 115 9.4 Arm workfl

22、ow . 116 9.5 Erase workflow 116 9.6 Abort Running Operation workflow 116 9.7 Firmware Update workflow . 117 9.8 Typed Block Data workflow . 122 9.8.1 Reading Typed Block Data workflow 123 9.8.2 Writing Typed Block Data workflow . 124 ANNEX A (normative) SDRAM and RCD Requirements for NVRDIMM-N Modul

23、es . 125 A.1 SDRAM and RCD requirements during a Catastrophic Save operation . 125 A.2 SDRAM and RCD requirements related to a Restore operation . 125 A.2.1 Overview . 125 A.2.2 Restore operation requirements . 125 A.2.3 Post-restore transition entry requirements . 126 A.2.4 Post-restore transition

24、exit requirements 131 ANNEX B (informative) revision history 135 B.1 Differences Between JESD245 (v1.0) and JESD245A (v2.0) 137 B.2 Differences Between JESD245A (v2.0) and this standard (JESD245B)(v2.1) . 135 JEDEC Standard No. 245B.01 -iv- FIGURES Figure 1: NVDIMM-N overview . 6 Figure 2: I2C Read

25、Byte transaction 8 Figure 3: I2C Write Byte transaction . 8 Figure 4: I2C Read Word transaction . 8 Figure 5: I2C Write Word transaction 9 Figure 6: I2C Block Read transaction 9 Figure 7: I2C Block Write transaction . 9 Figure 8: I2C paging mechanism . 11 TABLES Table 1: Required SPD fields 12 Table

26、 2: Firmware image header common format 26 Table 3: Firmware image header format 0 . 26 Table 4: Firmware image header format 1 . 27 Table 5: Temperature value bit definition . 30 Table 6: Mode register lower byte 32 Table 7: Mode register upper byte 32 Table 8: Page 0 register map categories 33 Tab

27、le 9: Page 0 register map . 34 Table 10: Major Revision and Minor Revision fields 37 Table 11: Reset Controller Scope field 40 Table 12. Page 1 register map categories 75 Table 13. Page 1 register map 75 Table 14. Page 2 register map categories 81 Table 15. Page 2 register map 82 Table 16. Page 3 re

28、gister map categories 98 Table 17. Page 3 register map 98 Table 18. Page 4 register map 109 Table 19. Page 5 register map 110 Table 20. Page 6 register map 111 Table 21. Page 7 register map 113 Table 22. Page 8 register map 113 Table 23. Page 9 register map 114 Table 24. MR0 requirements during a po

29、st-restore transition . 127 Table 25. MR1 requirements during a post-restore transition . 127 Table 26. MR2 requirements during a post-restore transition . 127 Table 27. MR3 requirements during a post-restore transition . 128 Table 28. MR4 requirements during a post-restore transition . 128 Table 29

30、. MR5 requirements during a post-restore transition . 129 Table 30. MR6 requirements during a post-restore transition . 129 Table 31. RCD requirements during a post-restore transition . 130 Table 32. Host reprogramming RCD function 0 control words after a post-restore transition 132 Table 33. Host r

31、eprogramming RCD function 1 control words after a post-restore transition 133 Table 34. Host reprogramming RCD function 4 control words after a post-restore transition 133 JEDEC Standard No. 245B.01 -v- FOREWORD This standard has been prepared by JEDEC. The purpose of this standard is definition of

32、a byte addressable energy backed function on a non-volatile dual in-line memory module (NVDIMM). This standard defines the feature set and commands implemented by the byte addressable energy backed function on an NVDIMM-N. INTRODUCTION An NVDIMM-N is a memory module that can be integrated into a sta

33、ndard platform. A Byte Addressable Energy Backed Function on a NVDIMM is designed to preserve data in the event of the power failure. A Byte Address Energy Backed Function is backed by a combination of SDRAM and non-volatile memory (e.g., NAND flash) on the NVDIMM-N. It operates at SDRAM speeds and

34、provides persistent storage by backing up the SDRAM contents into the non-volatile memory in the event of a power failure. This is made possible by an Energy Source (e.g., supercapacitor) which maintains charge on the module enabling back-up of data from SDRAM to the non-volatile memory, providing a

35、 storage-class memory solution. To be able to provide interoperability and the ability for platform and platform software (e.g., BIOS) to support NVDIMM-Ns from various manufacturers, standardization of the host to module interface, discovery mechanism, the feature set and command operations are req

36、uired, as described in this standard. JEDEC Standard No. 245B.01 -vi- JEDEC Standard No. 245B.01 Page 1 BYTE ADDRESSABLE ENERGY BACKED INTERFACE (From JEDEC Board Ballot JCB-17-15, formulated under the cognizance of the JC-45.6 Subcommittee on Hybrid Modules.) 1 SCOPE This standard specifies the hos

37、t and device interface for a DDR4 NVDIMM-N, which is a DIMM that achieves non-volatility by copying SDRAM contents into non-volatile memory (NVM) when host power is lost using an Energy Source managed by either the module or the host. Although this standard is targeted towards DDR4 NVDIMM only, it d

38、oes not preclude adoption of this standard by other implementations (e.g., DDR3 NVDIMM). 2 NORMATIVE REFERENCES The normative documents listed in this clause contain provisions that, through reference in this text, constitute provisions of this standard. For dated references, subsequent amendments t

39、o, or revisions of, any of these publications do not apply. However, parties to agreements based on this standard are encouraged to investigate the possibility of applying the most recent editions of the normative documents indicated below. For undated references, the latest edition of the normative

40、 document referred to applies. JESD21C, 4.20.28 DDR4 SDRAM Registered DIMM Design Specification, Revision 1.00 (August 2015) JESD21C, 4.1.2.L-4 Annex L: Serial Presence Detect (SPD) for DDR4 SDRAM Modules (DDR4 SPD Document Release 4) JESD21C, 4.1.2.L-5 Annex L: Serial Presence Detect (SPD) for DDR4

41、 SDRAM Modules (DDR4 SPD Document Release 5)(forthcoming) JESD21C, 4.1.6 Definitions of the EE1004-v 4 Kbit Serial Presence Detect (SPD) EEPROM and TSE2004av 4 Kbit SPD EEPROM with Temperature Sensor (TS) for Memory Module Applications JESD21C, 4.1.6-2 Definitions of the EE1004av 4 Kbit Serial Prese

42、nce Detect (SPD) EEPROM and TSE2004av 4 Kbit SPD EEPROM with Temperature Sensor (TS) for Memory Module Applications (forthcoming) JESD79-4A, DDR4 SDRAM (November 2013) JESD79-4B, DDR4 SDRAM (June 2017) JESD82-31, DDR4 Registering Clock Driver DDR4RCD01 (August 2016) JESD82-31A, DDR4 Registering Cloc

43、k Driver DDR4RCD02 (forthcoming) JESD82-32, DDR4 Data Buffer DDR4DB01 (August 2016) JESD82-32A, DDR4 Data Buffer DDR4DB02 (forthcoming) JESD245, Byte Addressable Energy Backed Interface (December 2015) JESD245A, Byte Addressable Energy Backed Interface (September 2016) JESD248 DDR4 NVDIMM-N Design S

44、pecification (Revision 1.0)(September 2016) JESD248A DDR4 NVDIMM-N Design Specification (forthcoming) I2C Bus Specification Revision 6 (4 April 2014) System Management Bus (SMBus) Specification Version 3.0 (20 December 2014) JEDEC Standard No. 245B.01 Page 2 3 TERMS AND DEFINITIONS For the purposes

45、of this standard, the terms and definitions given in the document included in clause 2 “Normative References” and this clause apply. 3.1 Acronyms DDR3 Double Data Rate version 3 DDR4 Double Data Rate version 4 DIMM Dual In-line Memory Module ES Energy Source I2C Inter IC (inter integrated circuit) L

46、COM LCOM Bus NVDIMM Non-volatile Dual In-line Memory Module NVDIMM-N NVDIMM with a Byte Addressable Energy Backed Interface function NVM Non-Volatile Memory NVRDIMM-N NVDIMM-N that is an RDIMM RCD Registering Clock Driver RDIMM Registered DIMM SDRAM Synchronous Dynamic Random Access Memory SMBus Sys

47、tem Management Bus SPD Serial Presence Detect JEDEC Standard No. 245B.01 Page 3 3.2 Terms and Definitions Abort: Operation that stops the currently running operation on the module. See 7.2.13. Arm: Operation that enables or disables trigger(s) for a Catastrophic Save operation. See 7.2.4. Catastroph

48、ic Save: Operation that copies the SDRAM contents into NVM when power is lost. The Catastrophic Save operation is started when an enabled trigger occurs or a write to an I2C register occurs. See 7.2.1. CKE Power Down mode: RCD mode in which all input buffers are disabled except for CK_t/CK_c, DCKEn,

49、 DRST_n, and sometimes DODTn and ERROR_IN_n. See JESD82-31A (DDR4RCD02). Clock Stopped Power Down mode: RCD mode in which all input buffers are disabled except for CK_t/CK_c. See JESD82-31A (DDR4RCD02). Device Managed Policy: Energy Source policy where the module manages the Energy Source used during the Catastrophic Save operation. Energy Source: A device that is capable of storing and providing energy to the module during a Catastrophic Save operation. See 7.2.13. Erase: Operation that deletes the previously saved SDRAM image in NVM. See 7.2.3. Fac