JEDEC JESD247-2016 Multi-wire Multi-level I O Standard.pdf

1、JEDEC SOLID STATE TECHNOLOGY ASSOCIATIONJESD247JUNE 2016JEDECSTANDARDMulti-wire Multi-level I/O StandardNOTICEJEDEC standards and publications contain material that has been prepared, reviewed, andapproved through the JEDEC Board of Directors level and subsequently reviewed and approvedby the JEDEC

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6、andard are met.Inquiries, comments, and suggestions relative to the content of this JEDEC standard orpublication should be addressed to JEDEC at the address below, or call (703) 907-7559 orwww.jedec.orgPublished byJEDEC Solid State Technology Association 20163103 North 10th StreetSuite 240 SouthArli

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8、cations online athttp:/www.jedec.org/Catalog/catalog.cfmPrinted in the U.S.A.All rights reservedPLEASE!DONT VIOLATETHELAW!This document is copyrighted by the JEDEC Solid State Technology Associationand may not be reproduced without permission.Organizations may obtain permission to reproduce a limite

9、d number of copies through entering into a license agreement. For information, contact:JEDEC Solid State Technology Association3103 North 10th Street, Suite 240SArlington, Virginia 22201or call (703) 907-7559JEDEC Standard No. 247-i-MULTI-WIRE MULTI-LEVEL I/O SPECIFICATIONContentsPage1 Scope 12 Mult

10、i-Wire Signaling Codes 22.1 General Architecture 22.2 Signal Levels 32.3 ENRZ Code Definition 42.4 CNRZ-5 Code Definition 53 Driver Specifications 73.1 Driver Test Load 83.2 Transmitter Return Loss 93.3 Common Mode Noise 93.4 Driver Linearity and Jitter Tests (Quaternary Drivers) 104 Receiver Specif

11、ications 124.1 Receiver Return Loss 134.2 Receiver Linearity and Jitter Tolerance Tests 135 HSpice Modeling 175.1 Multi-Wire Transmitters Using Quaternary Drivers 17JEDEC Standard No. 247-ii-JEDEC Standard No. 247Page 1MULTI-WIRE MULTI-LEVEL I/O SPECIFICATION(From JEDEC Board Ballot JCB-16-21, formu

12、lated under the cognizance of the JC-16 Committee on Interfaces Technology.)1 ScopeThis standard defines the DC and AC operating conditions, I/O impedances, termination characteristics, and compliance test methods of I/O drivers and receivers used in multi-wire, multi-level signaling interfaces. The

13、 multi-wire interfaces defined by this specification all utilize quaternary signal levels. Multi-wire signaling encodes n-bits of data per symbol onto an interface consisting of m-wires and utilizing quaternary signal levels. Differential signaling represents a simple multi-wire code where m = 2. Mu

14、lti-wire signaling interfaces with m 2 provide noise immunity and signal integrity characteristics similar to differential signals, but with higher throughput per wire.This standard defines (1) several multi-wire signaling codes that are supported by this standard, (2) specifications for I/O drivers

15、 and receivers that support these codes, and (3) compliance test methods used to test interfaces that utilize these I/O drivers and receivers. The specifications and compliance methods in this standard are intended to be sufficient to ensure the interoperability of devices from different manufacture

16、rs. Where possible, these test methods incorporate existing techniques used by the industry to test similar devices.This standard defines I/O drivers and receivers that are consistent with use for a minimal loss, low skew channel between two devices that are mounted immediately next to each other wi

17、thin a multi-chip module. Specifications that use this standard by reference will define the maximum baud rate and channel insertion loss based on the requirements of the target application. Specifications for applications which drive outside of a package to a DIMM may specify additional requirement

18、s for channel loss, channel skew, channel crosstalk, supply offset, transmit equalization, receive equalization, and skew tolerance. JEDEC Standard No. 247Page 22 Multi-Wire Signaling CodesMulti-wire signaling encodes n-bits of data per symbol onto an interface consisting of m-wires, where m 2. Thes

19、e wires are designated as w0, w1, . wm-1. Each wire is driven to one of s wire states, where each wire state corresponds to a unique single-ended signal level. For the codes listed in this specification, the sum of the wire states across the m wires is zero (i.e. common mode voltage is constant), an

20、d therefore the interface exhibits noise immunity qualities similar to that of a differential signal, but with higher throughput per wire.One method of classifying multi-wire signaling codes is by the values of n and m. The designation of nbmw, where n and m are replaced by their corresponding value

21、s, is a shorthand notation for specifying the number of bits encoded in each baud symbol and the number of interface wires on which the baud symbol is encoded, such that nbmw means that n bits are carried on m wires. The throughput efficiency of the code is defined as n/m (in units of bits per wire)

22、, which is a measure of the efficiency of the code.This section describes the multi-wire signaling codes supported by this standard.2.1 General ArchitectureThe general architecture of a multi-wire signaling interface is shown in Figure 1. The input to the encoder at the transmission end of the inter

23、face consists of n-bits of data, where n is determined by the multi-wire code being used. The encoder drives a unique codeword onto m-wires that is computed from the input data. The driver block puts the encoded value on the wires. Codewords are determined by the codebook for the code being used.At

24、the receive end of the interface, the Multi-wire Receiver (Rx) block converts the m-wire input to an n-wire output. This is accomplished by comparing the weighted average of groups of wires to the weighted average of other groups of wires as determined by a Linear Combination Table that is defined f

25、or the code. In the generic architecture, the Multi-wire Rx block may drive a decoder stage that decodes the data bits such that the d0to dn-1bits on the decoder outputs are equivalent to the data input to the encoder. The codes specified in this document do not require a decoder stage, in which cas

26、e the d0to dn-1bits are decoded directly by the Multi-wire Rx block.Encoderd0d1dn-1:w0w1wm-1:Multi-wire Rx:d0d1dn-1Decoder:Figure 1 Generic Architecture of a Multi-Wire Signaling InterfaceOne example of an implementation of the Multi-wire Rx block in Figure 1 is shown in Figure 2. The Rx Front End h

27、andles any amplification and equalization tasks. The Linear Combination matrix circuit generates weighted averages of groups of wires as determined by the Linear Combination Table defined for the code. This circuit may be implemented using a number of design approaches including passive resistor net

28、works or multi-input amplifier circuits. The corresponding averaged values are connected to the inputs of comparator circuits, and the output of these comparators are the decoded d0to dn-1bits. As noted previously, codes defined in this document do not require an additional digital decode stage.JEDE

29、C Standard No. 247Page 32.1 General Architecture (contd)Encoderd0d1dn-1:w0w1wm-1:Rx Front EndLinear Combination+-+-+-+-:d0d1dn-1Figure 2 Example Implementation of a Multi-Wire Signaling Interface2.2 Signal LevelsEach of the m wires of the multi-wire signaling interface is driven to one of s wire sta

30、tes, where s is determined by the multi-wire code being used. Each of the s wire states corresponds to a unique single-ended signal level.2.2.1 Quaternary Signal LevelsCodes for which s = 4 use quaternary I/O drivers which drive one of four signal levels. These signal levels are designated by the no

31、menclature +1, +1/3, -1/3, -1. Figure 3 illustrates the voltage relationship between these signal levels, where V+1indicates a wire at signal level +1, V+1/3indicates a wire at signal level +1/3, and so forth. V-1VCMV+1GNDMax absolute outputMin absolute outputV+1/3V-1/3Figure 3 Signal LevelsThe sing

32、le-ended voltage difference between the maximum V+1voltage and the minimum V-1voltage is defined as the Output Maximum Peak-to-Peak Voltage Swing (VSEpp).The voltage difference between each signal level and adjacent signal levels is roughly equal, such that the four signal levels are equally spaced

33、across the dynamic range of the driver.The common mode voltage (VCM) is computed as the average voltage of all wires of the interface. The multi-wire codes defined in this specification are constructed such that VCMis constant. This results in common mode and simultaneous switching noise immunity si

34、milar to that of differential signals.JEDEC Standard No. 247Page 42.3 ENRZ Code DefinitionThe ENRZ code maps 3 bits of data into codewords on 4 wires (3b4w), and uses quaternary signal levels (s = 4). The throughput efficiency of this code is 0.750.Table 1 provides the codebook which describes the m

35、apping between data bits and signal levels on the wires. Table 2 specifies the Linear Combination table containing the matrix of weights of each wire on the input to each comparator. A block diagram of an example implementation of an ENRZ receiver is shown in Figure 4.Table 1 ENRZ Code MapData Value

36、(d2, d1, d0)Wire States(w3, w2, w1, w0)Data Value(d2, d1, d0)Wire States(w3, w2, w1, w0)0 0 0 (-1, +1/3, +1/3, +1/3) 1 0 0 (-1/3, -1/3, -1/3, +1)0 0 1 (-1/3, +1, -1/3, -1/3) 1 0 1 (+1/3, +1/3, -1, +1/3)0 1 0 (-1/3, -1/3, +1, -1/3) 1 1 0 (+1/3, -1, +1/3, +1/3)0 1 1 (+1/3, +1/3, +1/3, -1) 1 1 1 (+1, -

37、1/3, -1/3, -1/3)Table 2 ENRZ Linear Combination TableContribution of each wire to comparator decodeComparator w3w2w1w0d0+1/2 +1/2 -1/2 -1/2d1+1/2 -1/2 +1/2 -1/2d2+1/2 -1/2 -1/2 +1/2Each comparator implements the calculation of:ciweight of wire j()signal level on wire j()j 0=m 1=If ciis greater than

38、0, then di= 1; if ciis less than 0, then di= 0. Simple and fast implementations of this operation are possible. ENRZ does not require a decoder stage after the comparator stage.w3+-VGAw2VGAw1VGAw0VGA+-+-+d0d2d1Figure 4 ENRZ Receiver Block Diagram ExampleJEDEC Standard No. 247Page 52.4 CNRZ-5 Code De

39、finitionThe CNRZ-5 code maps 5 bits of data into codewords on 6 wires (5b6w), and uses quaternary signal levels (s = 4). The throughput efficiency of this code is 0.833.Table 3 provides the codebook which describes the mapping between data bits and signal levels on the wires. Table 4 specifies the L

40、inear Combination table containing the matrix of weights of each wire on the input to each comparator. A block diagram of an example implementation of an CNRZ-5 receiver is shown in Figure 5.Table 3 CNRZ-5 Code MapData Value(d4, d3, d2, d1, d0)Wire States(w5, w4, w3, w2, w1, w0)Data Value(d4, d3, d2

41、, d1, d0)Wire States(w5, w4, w3, w2, w1, w0)0 0 0 0 0 (-1, -1/3, +1/3, +1, +1/3, -1/3) 1 0 0 0 0 (-1/3, -1, +1/3, +1, +1/3, -1/3)0 0 0 0 1 (-1/3, +1/3, +1, +1/3, -1/3, -1) 1 0 0 0 1 (+1/3, -1/3, +1, +1/3, -1/3, -1)0 0 0 1 0 (-1, -1/3, +1/3, -1/3, +1, +1/3) 1 0 0 1 0 (-1/3, -1, +1/3, -1/3, +1, +1/3)0

42、 0 0 1 1 (-1/3, +1/3, +1, -1, +1/3, -1/3) 1 0 0 1 1 (+1/3, -1/3, +1, -1, +1/3, -1/3)0 0 1 0 0 (-1, -1/3, +1/3, +1, -1/3, +1/3) 1 0 1 0 0 (-1/3, -1, +1/3, +1, -1/3, +1/3)0 0 1 0 1 (-1/3, +1/3, +1, +1/3, -1, -1/3) 1 0 1 0 1 (+1/3, -1/3, +1, +1/3, -1, -1/3)0 0 1 1 0 (-1, -1/3, +1/3, -1/3, +1/3, +1) 1 0

43、 1 1 0 (-1/3, -1, +1/3, -1/3, +1/3, +1)0 0 1 1 1 (-1/3, +1/3, +1, -1, -1/3, +1/3) 1 0 1 1 1 (+1/3, -1/3, +1, -1, -1/3, +1/3)0 1 0 0 0 (-1/3, +1/3, -1, +1, +1/3, -1/3) 1 1 0 0 0 (+1/3, -1/3, -1, +1, +1/3, -1/3)0 1 0 0 1 (+1/3, +1, -1/3, +1/3, -1/3, -1) 1 1 0 0 1 (+1, +1/3, -1/3, +1/3, -1/3, -1)0 1 0

44、1 0 (-1/3, +1/3, -1, -1/3, +1, +1/3) 1 1 0 1 0 (+1/3, -1/3, -1, -1/3, +1, +1/3)0 1 0 1 1 (+1/3, +1, -1/3, -1, +1/3, -1/3) 1 1 0 1 1 (+1, +1/3, -1/3, -1, +1/3, -1/3)0 1 1 0 0 (-1/3, +1/3, -1, +1, -1/3, +1/3) 1 1 1 0 0 (+1/3, -1/3, -1, +1, -1/3, +1/3)0 1 1 0 1 (+1/3, +1, -1/3, +1/3, -1, -1/3) 1 1 1 0

45、1 (+1, +1/3, -1/3, +1/3, -1, -1/3)0 1 1 1 0 (-1/3, +1/3, -1, -1/3, +1/3, +1) 1 1 1 1 0 (+1/3, -1/3, -1, -1/3, +1/3, +1)0 1 1 1 1 (+1/3, +1, -1/3, -1, -1/3, +1/3) 1 1 1 1 1 (+1, +1/3, -1/3, -1, -1/3, +1/3)Table 4 CNRZ-5 Linear Combination TableContribution of each wire to comparator decodeComparatorw

46、5w4w3w2w1w0d0+1/3 +1/3 +1/3 -1/3 -1/3 -1/3d10 0 0 -1 +1/2 +1/2d20 0 0 0 -1 +1d3+1/2 +1/2 -1 0 0 0d4+1 -1 0 0 0 0JEDEC Standard No. 247Page 62.4 CNRZ-5 Code Definition (contd)Each comparator implements the calculation of:ciweight of wire j()signal level on wire j()j 0=m 1=If ciis greater than 0, then

47、 di= 1; if ciis less than 0, then di= 0. Simple and fast implementations of this operation are possible. CNRZ-5 does not require a decoder stage after the comparator stage.w5+-VGAw4VGAw3VGAw2VGA+-+-+d4d3d0w1VGA-+d1-+d2w0VGAFigure 5 CNRZ-5 Receiver Block Diagram ExampleJEDEC Standard No. 247Page 73 D

48、river SpecificationsThis specification defines I/O drivers that are consistent with use for a minimal loss, low skew channel between two devices that are mounted immediately next to each other within a multi-chip module. Specifications that use this specification by reference will define the maximum

49、 baud rate and channel insertion loss based on the requirements of the target application. Specifications for applications which drive outside of a package to a DIMM may specify additional requirements for channel loss, channel skew, channel crosstalk, supply offset, transmit equalization, receive equalization, and skew tolerance. The multi-wire code interface transmitter consists of m driver I/O, where m is defined by the corresponding multi-wire code definition in 2. Each driver I/O shall meet the electrical and jitter specifications defined in Table