1、EINJEDEC STANDARD Test Criteria for the Wafer-Level Testing of Thin Dielectrics EINJICSD35-2 (Addendum No. 2 to EWJESD35) 1 FEBRUARY1996 I ELECTRONIC INDUSTRIES ASSOCIATION ENGINEERING DEPARTMENT EIA JESD35-2 76 3234600 0567590 54.5 U NOTICE EWJEDEC Standards and Publications contain material that h
2、as been prepared, progressively reviewed, and approved through the JEDEC Council level and subsequently reviewed and approved by the EIA General Counsel. EWJEDEC Standards and Publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purch
3、ases, faciiitating interchangeability and improvement of products, and assisting the purchaser is selecting and obtaining with minimurn delay the proper product for his particular need. Existence of such standards shall not in any respect preclude any member or nonmember of JEDEC !?om manufacturing
4、or seliing products not conforming to such standards, nor shall the existence of such standards preclude their voluntary use by those other than EIA members, whether the standard is to be used either domestidy or internationally. EWJEDEC Standards and Publications are adopted withou regard to whethe
5、r their adoption may involve patents or articles, materials, or processes. By such action, EWJEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the EWJEDEC Standards or Pubiications. The information included in EWJEDEC Standards an
6、d Publications represents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. Within the EWJEDEC organization there are procedures whereby an EWJEDEC Standard or Publication may be further processed and ultimately becomes an ANSE
7、IA Standard. Inquiries, comments, and suggestions relative to the content of this EWJEDEC Standard or Publication should be aressed to the JEDEC Executive Secretary at EIA Headquarters, 2500 Wilson Boulevard, Arlington, VA 22201. , Published by OELECTRONIC INDUSTRIES ASSOCIATION 1996 Engineering Dep
8、artment 2500 Wilson Boulevard Arlington, VA 2220 1 “Copyright“ does not apply to JEDEC member companies as they are free to duplicate this dominent in accordance with the latest revision of the JEDEC Publication 2 1 “Manua of Organization and Procedure“. PRICE: Please refer to the current Catalog of
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11、0-854-71 79, International (303) 397-7956 EIA JESD35-2 96 W 3234600 0567592 318 W ADDENDUMNo. 2 EINJEDEC STANDARD NO. 35-2 TEST CRITERIA FOR THE WAFER-LEVEL TESTING OF THIN DIELECTRICS Page . Foreword 111 1 Scope 1 2 Introduction 1 3 Current ramp end-point relaxation 1 4 Alternative voltage ramp end
12、 point determination 1 5 Considerations for choosing a failure criterion for JESD3 5 V-ramp method 2 6 Considerations for choosing a voltage increment for the JESD3 5 V-ramp method 4 -1- EIA JESD3.5-2 96 3234600 0567.593 254 ADDENDUM No. 2 EINJEDEC STANDARD NO. 35-2 Intentionally left blank -11- EIA
13、 JESD35-2 96 E 3234600 0567594 190 ADDENDUMNo. 2 EINJEDEC STANDARD NO. 35-2 TEST CRITERIA FOR THE WAFER-LEVEL TESTING OF TEIN DIELECTRICS FOREWORD This addendum includes test criteria to supplement JESD3 5. JESD3 5 describes procedures developed for estimating the overall integrity of thin oxides an
14、d as a tool for driving constant improvement in the thin oxide manufacturing process in the MOS integrated circuit manufacturing industry. Two test procedures are included in JESD3 5 : a voltage-ramp (V-Ramp) and a current-ramp (J-Ramp). It is important to realize that these procedures should not be
15、 interpreted as a means of predicting MOS integrated circuit failure rates but should be used rather for quick evaluation control techniques. Thus, no acceptance or rejection criteria are specified in association with these procedures. . -111- EIA JESD35-2 96 I 3234600 0567595 027 ADDENDUM No. 2 EIN
16、JEDEC STANDARD NO. 35-2 Intentionally lefi blank -iv- EIA JESD35-2 96 3234600 O567596 T63 = ADDENDUM No. 2 Page 1 EWJEDEC STANDARD NO. 35-2 TEST CRITERIA FOR THE WAFER-LEVEL TESTING OF THIN DIELECTRICS (From Council ballot JCB-95-3 1, formulated under the cognizance of JC-14.2 Committee on Wafer-Lev
17、el Reliability.) 1 Scope This addendum expands the usefulness of the JEDEC Standard No. 35 (JESD35) by detailing an alternative method of determining the end point of the voltage ramp test and expanding the range for determination of the end point for the current ramp test. 2 Introduction As JESD35
18、became implemented into production facilities on a variety of test structures and oxide attributes, a need arose to clan end point determination and to point out some of the obstacles that could be overcome by carefiil characterization of the equipment and test structures. 3 Current ramp end point r
19、elaxation 3.1 Background JESD35 specifies that the end point is determined by a fifieen percent drop in the voltage needed to force the next current step. 3.2 Relaxation for high resistance test structures A significant voltage drop will determine that the oxide has ruptured. Due to the high resista
20、nce (conductor resistance from bondprobe pads to the gate electrode) of some test structures, it may be necessary to reduce the required drop from fifieen percent to as low as five percent. 4 Alternative voltage ramp end point determination 4.1 Background JESD35 specifies that the end point is deter
21、mined by a current measurement of ten times the expected value at the voltage. EIA JESD35-2 96 9 3234600 0567597 9TT ADDENDUM No. 2 Page 2 EINJEDEC STANDARD NO. 35-2 4.2 Alternative method At a voltage value, determined by either obtaining a consistent measurable current or by exceeding the calculat
22、ed tunneling threshold, begin calculating and tracking the slope of voltage forced to the log of the current measured as determined by dividing the voltage by the log of the current. As present theoretical behavior predicts a constant slope, a slope change by a factor of 1.5 to 3 would indicate the
23、end point of the test. A maximum current for end point detection must be maintained to ensure that premature rupture is not occurring prior to the tunneling threshold. This value should be at least two times the maximum expected current during the test as determined by device characterization. 5 Con
24、siderations for choosing a failure criterion for JESD35 V-ramp method Although it is desirable that a universal failure criterion be chosen that is applicable to every implementation of the ramp test methods presented in JESD35, due to the wide range of oxide thickness, capacitor area, and the multi
25、plicity of test structure designs, conduction mechanisms, oxide processes, and test equipment sets, definition of a universal failure criterion is not practicabIe. Fortunately, round-robin experiments on structures with 20 nm oxides have shown that the specific implementation of test criteria is not
26、 critical to the accuracy and usefulness of the V-ramp test results in most cases. The approach taken in JESD35 assumes that a satisfactory stable oxide process is in place, that the stress will accurately determined the oxide breakdown . values from and will also notify the user, via the various re
27、ject categories, of any unexpected deviation fiom the established data base (considered normal behavior for the process). Failure criteria that achieve these objectives are considered equivalent to the specified criterion. The use of multiple reject categories and the inherent notification of anomal
28、ous, possibly invalid test results is one of the major benefits of the JESD35 (J-ramp or V-ramp). Many possible failure criteria were considered during the development of the V-ramp specification and a current multiplier (CM) was selected, in spite of the increased difficulty of making the failure d
29、etermination. The CM method is capable of detecting the greatest variety of known anomalous behaviors and assumes no particular conduction mechanism; although, Fowler-Nordheim conduction is expected to be the dominant conduction mechanism for SiO, at moderate to high applied fields, i.e., 6 MV/cm. A
30、 CM of 10 was chosen as a reasonable increase for 20 nm oxides with a voltage step of 100 mV. Smaller increases would be expected for smaller voltage steps; however test structures that go to-low resistance at failure will exhibit a 10 X increase for all but the smallest of voltage steps. EIA JESD35
31、-2 96 E 323Yb00 05b759 36 = ADDENDUM No. 2 Page 3 EINJEDEC STANDARD NO. 35-2 There is an interaction between the CM failure criterion and the test system compliance at high fields. This can result in the inability to achieve the failure criterion as the conduction current approaches within one order
32、 of magnitude of the system compliance limit. This occurrence will be assigned to the “Masked Catastrophic“ reject category. Initial current of 1 pA was chosen to identify gross shorts and avoid issues of capacitor area and measurement resolution dependencies. This specification allows the possibili
33、ty that a structure could pass initial and final screen yet fail for the current factor criterion. Such a device would be assigned to the “Noncatastrophic“ reject category. Implementation of the CM failure criterion requires careful characterization of the I-V behavior of the particular test structu
34、re (including both “good“ and “bad“ characteristics) under V-ramp stress conditions, storing the nominal I-V curve in a lookup table and verifying the appropriate current factor. The V-ramp method can then be performed while making point-by-point comparisons of the stress and reference (lookup table
35、) data to determine the reject or failure status of the structure under test. Many implementations of so called “JEDEC standard V-ramp“ methods do not use this reference-based failure criterion. The CM may need to be adjusted depending on the specific test implementation and type of structure used.
36、The value must be large enough to ailow for expected process variation and measurement system noise/resolution, yet small enough to catch the expected slope change .of a breakdown event and any transient anomalies that may occur. Rapid self healing breakdown events are considered to be undetectable
37、by this type of stepped and sampled test method. Other CM failure criteria implementation (such as maximum currenilcompliance limit) have been used successfully but may not detect unusual conduction mechanisms or transient events such as self-healing ruptures, progressive ruptures or defect induced
38、trapping. Alternative failure criteria based on comparison of sequential readings rather than previously established, historical behavior will not be capable of detecting gradual shifts in I-V performance over time. EIA JESD35-2 96 m 3234600 O567599 772 m ADDENDUM No. 2 Page 4 EINJEDEC STANDARD NO.
39、35-2 6 Considerations for choosing a voltage increment for the JESD35 V-ramp method When choosing a voltage increment for the V-ramp the following items should be considered: (1) Since the breakdown values are reported at the last passing stress condition, smaller steps will produce more accurate re
40、sults. Larger steps will result in lower breakdown values because some portion of the survival data that occurs during the final step is discarded. (2) Due to the finite response time of the test structurehest system to the breakdown event, some measurements will occur after the onset of rupture but
41、 before the failure criterion is met. The resulting breakdown values will be overestimated depending on the number of readings taken before exceeding the failure criterion (progressive breakdown can produce a similar result). The fiequency of this occurrence increases with decreasing step size. Qbd
42、is particularly sensitive under these conditions due to the high conduction current under these conditions. A plot of Qbd vs Vbd may be useful in identi%ng this type of occurrence. A discontinuity in the high voltage behavior, showing abnormally Qbd values, will result. - EIA JESD35-2 96 U 3234600 0567600 214 =
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