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本文(JEDEC JESD35-A-2001 Procedure for the Wafer-Level Testing of Thin Dielectrics《薄电介质的Wafer-Level测试程序》.pdf)为本站会员(priceawful190)主动上传,麦多课文库仅提供信息存储空间,仅对用户上传内容的表现方式做保护处理,对上载内容本身不做任何修改或编辑。 若此文所含内容侵犯了您的版权或隐私,请立即通知麦多课文库(发送邮件至master@mydoc123.com或直接QQ联系客服),我们立即给予删除!

JEDEC JESD35-A-2001 Procedure for the Wafer-Level Testing of Thin Dielectrics《薄电介质的Wafer-Level测试程序》.pdf

1、JEDECSTANDARDProcedure for the Wafer-Level Testingof Thin DielectricsJESD35-A(Revision of JESD35)APRIL 2001JEDEC Solid State technology AssociationNOTICEJEDEC standards and publications contain material that has been prepared, reviewed, andapproved through the JEDEC Board of Directors level and subs

2、equently reviewed and approvedby the EIA General Counsel.JEDEC standards and publications are designed to serve the public interest through eliminatingmisunderstandings between manufacturers and purchasers, facilitating interchangeability andimprovement of products, and assisting the purchaser in se

3、lecting and obtaining with minimumdelay the proper product for use by those other than JEDEC members, whether the standard is tobe used either domestically or internationally.JEDEC standards and publications are adopted without regard to whether or not their adoptionmay involve patents or articles,

4、materials, or processes. By such action JEDEC does not assumeany liability to any patent owner, nor does it assume any obligation whatever to parties adoptingthe JEDEC standards or publications.The information included in JEDEC standards and publications represents a sound approach toproduct specifi

5、cation and application, principally from the solid state device manufacturerviewpoint. Within the JEDEC organization there are procedures whereby an JEDEC standard orpublication may be further processed and ultimately become an ANSI/EIA standard.No claims to be in conformance with this standard may

6、be made unless all requirements stated inthe standard are met.Inquiries, comments, and suggestions relative to the content of this JEDEC standard orpublication should be addressed to JEDEC Solid State Technology Association, 2500 WilsonBoulevard, Arlington, VA 22201-3834, (703)907-7560/7559 or www.j

7、edec.orgPublished byJEDEC Solid State Technology Association 20002500 Wilson BoulevardArlington, VA 22201-3834This document may be downloaded free of charge, however EIA retains thecopyright on this material. By downloading this file the individual agrees not tocharge for or resell the resulting mat

8、erial.PRICE: Please refer to the currentCatalog of JEDEC Engineering Standards and Publications or call Global EngineeringDocuments, USA and Canada (1-800-854-7179), International (303-397-7956)Printed in the U.S.A.All rights reservedPLEASE!DONT VIOLATETHELAW!This document is copyrighted by the Elec

9、tronic Industries Alliance and may not bereproduced without permission.Organizations may obtain permission to reproduce a limited number of copiesthrough entering into a license agreement. For information, contact:JEDEC Solid State Technology Association2500 Wilson BoulevardArlington, Virginia 22201

10、-3834or call (703) 907-7559JEDEC Standard No. 35-A-i-PROCEDURE FOR THE WAFER-LEVEL TESTING OF THIN DIELECTRICSCONTENTSPageForeword ii1Scope 12 Introduction 12.1 Overview 12.1 Choosing the appropriate stress procedures 13 Terms and definitions 24 V-ramp test procedure 44.1 Test configuration 44.2 V-R

11、amp input and output parameters 44.3 Pre-Ramp oxide current test 64.4 Ramp voltage stress 64.5 Post-ramp oxide current test 104.6 Data recording 114.7 Oxide failure categories 115 J-Ramp test procedure 125.1 Test configuration 125.2 J-Ramp input and output parameters 125.3 Pre-Ramp oxide test 145.4

12、J-Ramp stress test 175.5 Bounded J-Ramp 195.6 Post-ramp oxide test 215.7 Data recording 215.8 Oxide failure categories 226 References 23Annex A Supplemental data analysis 24A.1 Overview 24A.2 Data analysis 24A.3 Defect source analysis 27Annex B Supplemental Sampling plan statistics 29B.1 Overview 29

13、B.2 Determining an acceptable defect density level 30B.3 Sampling required to demonstrate defect densities 32B.4 Determining defect density from a test result 34B.5 Ensuring acceptable edge defect densities 35B.6 Examples for use of defect density curves 35Annex C Fowler-Nordheim tunneling current 4

14、0C.1 Fowler-Nordheim 40Figures4.1 Basic voltage-ramp flow diagram 74.2 Detailed voltage-ramp flow diagram 84.3 Diagram of typical voltage-ramp test 95.1 Basic J-Ramp flow diagram 155.2 Detailed J-Ramp flow diagram 165.3 Diagram of typical J-Ramp test 185.4 Detailed bounded J-Ramp flow diagram 20Tabl

15、es4.1 Input parameters for the V-Ramp test procedure 54.2 Output parameters for the V-Ramp test procedure 64.3 Oxide failure categories 125.1 Input parameters for the J-Ramp test procedure 135.2 Output parameters for the J-Ramp test procedure 135.3 Oxide failure categories 22JEDEC Standard No. 35-A-

16、ii-PROCEDURE FOR THE WAFER-LEVEL TESTING OF THIN DIELECTRICSForewordThis document is intended for use in the MOS Integrated Circuit manufacturing industryfabrication processing and test and describes procedures developed for estimating the overallintegrity of thin oxides. Three basic test procedures

17、 are described, the Voltage-Ramp (V-Ramp),the Current-Ramp (J-Ramp) and the Constant Current (Bounded J-Ramp) test. Each test isdesigned for simplicity, speed and ease of use.The purpose of this document is to describe oxide test techniques for quick evaluation andcontrol of oxide fabrication techni

18、ques. It does not specify acceptance or rejection criteria forany of the described procedures and therefore not intended to be used to predict MOS IntegratedCircuit failure rates.The material contained within this publication is formulated under the cognizance of JEDECJC-14.2 Committee and approved

19、by the JEDEC Board of Directors.JEDEC Standard No. 35-APage 1PROCEDURE FOR THE WAFER-LEVEL TESTING OF THIN DIELECTRICS(From JEDEC Board Ballot JCB-99-24, formulated under the cognizance of JEDEC JC-14.2Subcommittee on Wafer Level Reliability)1ScopeThis document defines test procedures for the V-Ramp

20、, J-Ramp and the Bounded J-Ramp oxideintegrity tests. Included within this document are recommended data analysis methods andguidelines for statistical sampling.2 Introduction2.1 OverviewThe thin dielectric integrity of MOS devices and circuits is an important reliability concern.Historically, thin

21、oxide reliability has been driven by oxide defects. In general the intrinsic oxidelifetime is much longer than the use requirements, but defects can significantly reduce oxidelifetime. The procedures described herein were developed to estimate the integrity of a thinoxide and as a tool for driving c

22、onstant improvement in the thin oxide process.The test procedures described within this document should not used to predict failure rates of asemiconductor product but rather tools for process control of oxide integrity. In actual practicethe oxide reliability of a semiconductor product is a complic

23、ated function of individual transistorduty cycles, transient voltage variation, the gate graded potential and series resistance in the gateload. These parameters are not considered within this document.2.2 Choosing the appropriate stress proceduresThree test procedures are described within this docu

24、ment; a ramped voltage (V-Ramp), a rampedcurrent (J-Ramp) and a constant current (Bounded J-Ramp) test. Each of these procedures isdesigned for simplicity, speed and ease of use and can be implemented at each point in theprocess from oxide formation onward.The voltage ramp test (V-Ramp) starts at th

25、e use condition voltage or lower and ramps linearlyfrom this value until oxide breakdown. The current density ramp test (J-Ramp) begins at a lowvalue of current and ramps exponentially until oxide breakdown. The constant current test(Bounded J-Ramp) only rises to a specified current density level an

26、d it is maintained there untiloxide breakdown.JEDEC Standard No. 35-APage 22 Introduction (contd)2.2 Choosing the appropriate stress procedures (contd)V-Ramp tests are often applied to oxides where characterization of the defects at lower electricfields is important. On the other hand, since the J-R

27、amp begins at a voltage sufficient to producemeasurable amounts of tunneling current (typically much higher than the starting voltage for aV-Ramp test), it can provide only very coarse segregation of the low field breakdowns, but canprovide fine segregation of the high field breakdowns in much less

28、time than a V-Ramp test.J-Ramp tests are often applied to small area test structures as a means of controlling an establishedprocess.The Bounded J-Ramp (constant current) provides a very repeatable charge-to-breakdown (Qbd)measurement where the current/current density is ramped to a specified level

29、and then held untilbreakdown. The majority of the charge-to-breakdown in both the J-ramp and V-ramp tests occursduring the last few steps of testing. Thus timing, measurement conditions, step size can greatlyinfluence the value of Qbdusing these tests. With the bounded J-Ramp, once a constant curren

30、tvalue is reached, each increment contributes approximately the same charge to the total value of Qbdreducing the dependence on testing equipment. For these reasons, comparisons of Qbdshould beperformed using the Bounded J-Ramp.As a result of this difference in the speed and field resolution of the

31、above tests, there areapplications where each one might be more appropriate. The J-Ramp test typically takes less timeto determine defect density than a V-Ramp test. So the J-Ramp might be favored if large samplesize and throughput are important. The Bounded J-Ramp has better Qbdresolution. When low

32、 fieldextrinsic information is desired, then the V-Ramp may be a better choice. However, all of thesetests will allow resolution between defective (extrinsic) and non-defective (intrinsic) oxide teststructures.3 Terms and definitionsThe following symbols are used in this document. They have been lis

33、ted alphabetically for theconvenience of the reader.aoxide(cm2): Thin oxide gate pliance: The test equipment maximum current or voltage forcing capability. Often the usercan specify a compliance limit for a particular test. In this case the test instrumentation will notexceed this compliance limit d

34、uring the test procedure.JEDEC Standard No. 35-APage 33 Terms and definitions (contd)E (V/cm): E is the estimated oxide electric field. The general formula for E is:E = V / Tox,where V is the voltage and Toxis the estimated oxide thickness, as determined by aconsistent, documented method. The method

35、 (or a reference to the documented standard)must be included in the data report.Ebd (V/cm): The estimated oxide electric field just prior to the detection of breakdown (seeAnnex C).J (A/cm2): The oxide current density calculated by dividing the oxide current by the oxide area(Aoxide).Qbd (Coulombs):

36、 The accumulated charge passing through the oxide prior to breakdown isdefined as:!“bdtttbddttIQ0)(2)where t is time. The Qbdiscalculated as the integral from t = 0 to t = tbdwhere tbdis the lastmeasurement time at the step just prior to breakdown.qbd (C/cm2): The accumulated charge density, passing

37、 through the oxide at the detection ofbreakdown. Calculated as:AQqoxidebdqb“ (3)JEDEC Standard No. 35-APage 44 V-ramp test procedure4.1 Test configurationThe voltage-ramp (V-RAMP) test is performed on an oxide capacitor by applying a voltagebetween the gate electrode (typically polysilicon or alumin

38、um) and bulk electrode (typicallysubstrate or well) with all other diffusions and wells connected to substrate. It is recommended thatthe gate voltage polarity should bias the device into accumulation to minimize inversion capacitanceeffects but inversion can be used if the test structure design or

39、conditions such as heat or lightillumination provides a source of minority carriers to the inverted layer. Although these proceduresare applicable to measurements at other operating temperatures these procedures are typicallyperformed at room temperature (25 + 5 C).The oxide capacitor test structure

40、 should be designed so that parasitic series resistance effects areminimized. High series resistance can severely impact the accuracy of these measurements. This isespecially true for high current oxide breakdowns where large series resistance voltage drops occur.A second requirement of the capacito

41、r test structure is that probe pads should not exist over theoxide under stress. Mechanical stress caused by probing pads over oxides can result in devicedamage and inaccurate defect density measurements.The following sections describe the details of the V-Ramp measurement. This measurement isperfor

42、med in three parts. First, a pre-oxide current test checks for an initial failure. After this test,a voltage ramp is performed until oxide breakdown. Finally a post oxide current test determines thefinal state of the oxide structure.4.2 V-Ramp input and output parametersThe V-Ramp input and output p

43、arameters are listed in Table 4.1 and Table 4.2, respectively.Table 4.1 defines the input parameters required to set up the V-Ramp test and also defines inputparameter guidelines. Table 4.2 defines the V-Ramp output parameters. Optional outputparameters include Vcritand Vbox(see Table 4.2 for defini

44、tions).JEDEC Standard No. 35-APage 54.2 V-Ramp input and output parameters (contd)Table 4.1 Input parameters for the V-Ramp test procedureInput Units CommentsVuseV Oxide voltage under normal operating conditions, typically the power supplyvoltage of the process. This voltage is used to measure pre-

45、and post voltageramp oxide current.IinitA Oxide breakdown failure current when biased at Vuse. Typical value is#$%&/cm2and may change depending on oxide area. For maximumsensitivity the specified value should be well above the worse case oxidecurrent of a “good” oxide and well above the “noise level

46、“ of themeasurement system. Higher values must be specified for ultra-thin oxidesbecause of direct tunneling effects.VstartV Starting voltage for voltage ramp. Typical value is Vuse.VstepV Voltage ramp step height. This value has a maximum value of 0.1 MV/cm.For example, the maximum value can be cal

47、culated using Tox*0.1 MV/cm,where Tox is in units of centimeters. This is 0.1 V for a 10 nm oxide.tsteps Voltage ramp step time. The Voltage ramp step time is determined from theRamp-rate and Vstep. The step time should be less than or equal to 0.1sec.Ramp-rate V/s The Ramp-rate is specified at 1.0

48、MV/cm per second. For example, the ramp-rate should be set to Tox*1.0 MV/cm-sec where Tox is in centimeters. This is1 V/s for a 10.0 nm oxide.IcritA At least 10 times the test system current measurement noise floor. This oxidecurrent is the minimum value used in determining the change of slopebreakd

49、own criteriaIboxA An optional measured current level for which a stress voltage is recorded.This value provides an additional point on the current-voltage curve. Atypical value is 1 %A.IbdA Oxide current breakdown criteria. Ibdis obtained from I-V curves and is theoxide current at the step just prior to breakdown.qmaxC/cm2Maximum accumulated oxide charge per oxide area. Used to terminate a testwhere breakdown occurred but was not detected during the test.VmaxV The maximum voltage limit for the voltage ramp. This limit is specified at30 MV/cm for oxides less than 20 nm th

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