JEDEC JESD47J 01-2017 Stress-Test-Driven Qualification of Integrated Circuits (Minor Revision of JESD47J August 2017).pdf

1、JEDEC STANDARD Stress-Test-Driven Qualification of Integrated Circuits JESD47J.01 (Revision of JESD47J, August 2017) SEPTEMBER 2017 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board

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9、 Association 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 or refer to www.jedec.org under Standards-Documents/Copyright Information. JEDEC Standard No. 47J.01 Page 1 STRESS DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS (From JEDEC Board Ballot, JCB-17-09, formulated under the cogniz

10、ance of the JC14.3 Subcommittee on Silicon Devices Reliability Qualification and Monitoring.) 1 Scope This standard describes a baseline set of acceptance tests for use in qualifying electronic components as new products, a product family, or as products in a process which is being changed. These te

11、sts are capable of stimulating and precipitating semiconductor device and packaging failures. The objective is to precipitate failures in an accelerated manner compared to use conditions. Failure Rate projections usually require larger sample sizes than are called out in qualification testing. For g

12、uidance on projecting failure rates, refer to JESD85 Methods for Calculating Failure Rates in Units of FITs. This qualification standard is aimed at a generic qualification for a range of use conditions, but is not applicable at extreme use conditions such as military applications, automotive under-

13、the-hood applications, or uncontrolled avionics environments, nor does it address 2ndlevel reliability considerations, which are addressed in JEP150. Where specific use conditions are established, qualification testing tailored to meet those specific requirements can be developed, using JESD94 that

14、will result in a better optimization of resources. This set of tests should not be used indiscriminately. Each qualification project should be examined for: a) Any potential new and unique failure mechanisms. b) Any situations where these tests/conditions may induce invalid or overstress failures. I

15、f it is known or suspected that failures either are due to new mechanisms or are uniquely induced by the severity of the test conditions, then the application of the test condition as stated is not recommended. Alternatively, new mechanisms or uniquely problematic stress levels should be addressed b

16、y building an understanding of the mechanism and its behavior with respect to accelerated stress conditions (Ref. JESD91, “Method for Developing Acceleration Models for Electronic Component Failure Mechanisms” and JESD94, “Application Specific Qualification using Knowledge Based Test Methodology”).

17、Consideration of PC board assembly-level effects may also be necessary. For guidance on this, refer to JEP150, Stress-Test-Driven Qualification of and Failure Mechanisms Associated with Assembled Solid State Surface-Mount Components. This document does not relieve the supplier of the responsibility

18、to assure that a product meets the complete set of its requirements. JEDEC Standard No. 47J.01 Page 2 2 Reference documents The revision of the referenced documents shall be that which is in effect on the date of the qualification plan. 2.1 Military MIL-STD-883, Test Methods and Procedures for Micro

19、electronics MIL-PRF 38535 2.2 Industrial UL94, Tests for Flammability of Plastic Materials for Parts in Devices and Appliances. ASTM D2863, Flammability of Plastic Using the Oxygen Index Method. IEC Publication 695, Fire Hazard Testing. J-STD-020, Joint IPC/JEDEC Standard, Moisture/Reflow Sensitivit

20、y Classification for Nonhermetic Solid State Surface-Mount Devices. JP-001, Foundry Process Qualification Guidelines (Wafer Fabrication Manufacturing Sites). JS-001, Joint JEDEC/ESDA Standard for Electrical Discharge Sensitivity Test - Human Body Model (HBM) Component Level JS-002, ESDA/JEDEC Joint

21、Standard for Electrostatic Discharge Sensitivity Testing Charged Device Model (CDM) Device Level J-STD-002, Solderability Tests for Component Leads, Terminations, Lugs, Terminals and Wires JESD22 Series, Reliability Test Methods for Packaged Devices JESD46, Guidelines for User Notification of Produc

22、t/process Changes by Semiconductor Suppliers. JESD69, Information Requirements for the Qualification of Silicon Devices. JESD74, Early Life Failure Rate Calculation Procedure for Electronic Components. JESD78, IC Latch-Up Test. JESD85, Methods for Calculating Failure Rates in Units of FITs. JESD86,

23、Electrical Parameters Assessment. JESD94, Application Specific Qualification using Knowledge Based Test Methodology. JESD91, Methods for Developing Acceleration Models for Electronic Component Failure Mechanisms. JEP122, Failure Mechanisms and Models for Semiconductor Devices. JEP143, Solid State Re

24、liability Assessment Qualification Methodologies. JEP150, Stress-Test-Driven Qualification of and Failure Mechanisms Associated with Assembled Solid State Surface-Mount Components. JESD201, Environmental Acceptance Requirements for Tin Whisker Susceptibility of Tin and Tin Alloy Surface Finishes JED

25、EC Standard No. 47J.01 Page 3 3 General requirements 3.1 Objective The objective of this procedure is to ensure that the device to be qualified meets a generally accepted set of stress test driven qualification requirements. Qualification is aimed at components used in commercial or industrial opera

26、ting environments. 3.2 Qualification family While this specification may be used to qualify an individual component, it is designed to also qualify a family of similar components utilizing the same fabrication process, design rules, and similar circuits. The family qualification may also be applied

27、to a package family where the construction is the same and only the size and number of leads differs. Interactive effects of the silicon and package shall be considered in applying family designations. 3.3 Lot requirements Test samples shall comprise representative samples from the qualification fam

28、ily. Manufacturing variability and its impact on reliability shall be assessed. Where applicable the test samples will be composed of approximately equal numbers from at least three (3) nonconsecutive lots. Other appropriate means may be used to evaluate manufacturing variability. Sample size and pa

29、ss/fail requirements are listed in Tables 1-3. Tables A and B give guidance on translating pass/fail requirements to larger sample sizes. Generic data and larger sample sizes may be employed based upon a Chi Squared distribution using a total percent defective at a 90% confidence limit for the total

30、 required lot and sample size. ELFR requirements shall be assessed at a 60% confidence level as shown in Table B. If a single unique and expensive component is to be qualified, a reduced sample size qualification may be performed using 1/3 the sample size listed in the qualification tables. 3.4 Prod

31、uction requirements All test samples shall be fabricated and assembled in the same production site and with the same production process for which the device and qualification family will be manufactured in production. Samples need to be processed through the full production process including burn-in

32、, handling, test, and screening. 3.5 Reusability of test samples Devices that have been used for nondestructive qualification tests may be used to populate other qualification tests. Devices that have been used in destructive qualification tests may not be used in subsequent qualification stresses e

33、xcept for engineering analysis. Non-destructive qualification tests are: Early Life Failure Rate, Electrical Parameters Assessment, External Visual, System Soft Error, and Physical Dimensions. JEDEC Standard No. 47J.01 Page 4 3.6 Definition of electrical test failure after stressing Post-stress elec

34、trical failures are defined as those devices not meeting the individual device specification or other criteria specific to the environmental stress. If the cause of failure is due to causes unrelated to the test conditions, the failure shall be discounted. 3.7 Required stress tests for qualification

35、 Table 1, Table 2, and Table 3 list the qualification requirements for new components. Table 2 and Table 3 are differentiated by package type, but these are not exclusively packaging tests. Interactive effects of the packaging on the silicon also drive the need for tests in Table 2 and Table 3. Powe

36、r supply voltage for biased reliability stresses should be Vccmax or Vddmax as defined in the device datasheet as the maximum specified power supply operating voltage, usually the maximum power supply voltage is 5% to 10% higher than the nominal voltage. Some tests such as HTOL may allow for higher

37、voltages to gain additional acceleration of stress time. JEP122 can provide guidance for accelerating common failure mechanisms. Table 4 lists the required stresses for a qualification family or category of change. Interactive effects from the unchanged aspects of both the silicon and packaging must

38、 be assessed. 3.8 Pass/Fail criteria Passing all appropriate qualification tests specified in Table 1, Table 2, and Table 3, either by performing the test, showing equivalent data with a larger sample size, or demonstrating acceptable generic data (using an equivalent total percent defective at a 90

39、% confidence limit for the total required lot and sample size), qualifies the device per this document. When submitting test data from generic products or larger sample sizes to satisfy the Table 1, Table 2, and Table 3 qualification requirements of this document, the number of samples and the total

40、 number of defective devices occurring during those tests must satisfy 90% confidence level of a Poisson exponential binomial distribution, as defined in MIL-PRF 38535. MIL-PRF 38535 is available for free from http:/www.dscc.dla.mil/Programs/MilSpec/listdocs.asp?BasicDoc=MIL-PRF-38535. The minimum n

41、umber or samples for a given defect level can be approximated by the formula: N = 0.5 2(2C+2, 0.1) 1/LTPD 0.5 + C where C = accept #, N=Minimum Sample Size, 2 is the Chi Squared distribution value for a 90% CL, and LTPD is the desired 90% confidence defect level. Table A is based upon this formula,

42、but in some cases the sample sizes are slightly smaller than MIL-PRF-38535. JEDEC Standard No. 47J.01 Page 5 3.8 Pass/Fail criteria (contd) Acceptance Number LTPD LTPD LTPD LTPD LTPD LTPD LTPDC 1075321.510 22 32 45 76 114 153 2301 38 55 77 129 194 259 3892 53 76 106 177 266 355 5323 67 96 134 223 33

43、4 446 6684 80 115 160 267 400 533 8005 94 133 186 310 465 619 9286 107 152 212 352 528 703 10547 119 170 237 394 590 786 11798 132 188 262 435 652 868 13019 144 205 287 476 713 949 142310 157 223 311 516 773 1030 154311 169 240 335 556 833 1110 166312 181 258 359 596 893 1189 1782Table A Sample Size

44、 for a Maximum % Defective at a 90% Confidence LevelEXAMPLE: Using generic data for HTOL with a requirement of 0 rejects from 230 samples. If 700 samples of generic data are available, the maximum number of failures that will meet the qualification test requirement is 3 failures from the LTPD=1 colu

45、mn. 4 Qualification and requalification 4.1 Qualification of a new device New or redesigned products (die revisions) manufactured in a currently qualified qualification family may be qualified using one (1) wafer/assembly lot. Electrical parameter assessment is one of the most important tests to run

46、. 4.2 Requalification of a changed device Requalification of a device will be required when the supplier makes a change to the product and/or process that could potentially impact the form, fit, function, quality and/or reliability of the device. The guidelines for requalification tests required are

47、 listed in Table 4. 4.2.1 Process change notification Supplier will meet the requirements of JESD46 “Guidelines for User Notification of Product/Process Changes by Semiconductor Suppliers“ for product/process notification changes. 4.2.2 Changes requiring requalification All product/process changes s

48、hould be evaluated against the guidelines listed in Table 4. JEDEC Standard No. 47J.01 Page 6 4.2 Requalification of a changed device (contd) 4.2.3 Criteria for passing requalification Table 4 lists qualification plan guidelines for performing the appropriate Table 1, Table 2, and Table 3 stresses.

49、Failed devices should be analyzed for root cause and correction; only a representative sample needs to be analyzed. Acceptable resolution of root cause and successful demonstration of corrective and preventive actions will constitute successful requalification of the device(s) affected by the change. The part and/or the qualification family can be qualified as long as containment of the problem is demonstrated until corrective and preventive actions are in place. 5 Qualification tests 5.1 General tests Test details are given in Table 1, Table 2, and Table 3. Not all tes