JEDEC JESD51-32-2010 EXTENSION TO JESD51 THERMAL TEST BOARD STANDARDS TO ACCOMMODATE MULTI-CHIP PACKAGES.pdf

1、JEDEC STANDARD EXTENSION TO JESD51 THERMAL TEST BOARD STANDARDS TO ACCOMMODATE MULTI-CHIP PACKAGES JESD51-32 DECEMBER 2010 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Direc

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5、und approach to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may be further processed and ultimately become an ANSI standard. No claims to be in confor

6、mance with this standard may be made unless all requirements stated in the standard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC at the address below, or refer to www.jedec.org under Standards and Documents f

7、or alternative contact information. Published by JEDEC Solid State Technology Association 2010 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 This document may be downloaded free of charge; however JEDEC retains the copyright on this material. By downloading this file the individual

8、 agrees not to charge for or resell the resulting material. PRICE: Contact JEDEC Printed in the U.S.A. All rights reserved PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by JEDEC and may not be reproduced without permission. Organizations may obtain permission to reproduce a limited numb

9、er of copies through entering into a license agreement. For information, contact: JEDEC Solid State Technology Association 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 or refer to www.jedec.org under Standards and Documents for alternative contact information. JEDEC Standard No. 5

10、1-32 Page 1 EXTENSION TO JESD51 THERMAL TEST BOARD STANDARDS TO ACCOMMODATE MULTI-CHIP PACKAGES (From JEDEC Board Ballot JCB-10-63, formulated under the cognizance of the JC-15 Committee on Thermal Characterization.) 1 Scope This document addresses the need for extending the existing thermal test bo

11、ard standards to accommodate the potential of higher electrical connection needs of multi-chip packages (MCPs) and the associated wire routing to implement these connections. The extensions described below also are applicable to single chip packages needing more than 36 electrical connections for th

12、e test. 2 Normative References The following documents are recommended reading for reference and thermal test board standard description purposes: 1 JESD51-3, “Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages” 2 JESD51-5, “Extension of Thermal Test Board Standards for

13、Packages with Direct Thermal Attachment Mechanisms” 3 JESD51-7, “High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages” 4 JESD51-9, “Test Boards for Area Array Surface Mount Package Thermal Measurements” 5 JESD51-10, “Test Boards for Through-Hole Perimeter Leaded Package T

14、hermal Measurements” 6 JESD51-11, “Test Boards for Through-Hole Area Array Leaded Package Thermal Measurements” JEDEC Standard No. 51-32 Page 2 3 Extensions While the 36 connections of the 18/36 pin edge connector referenced in the JESD51 series of documents 1-6 has proved adequate for the large maj

15、ority of single chip packages, there is the likelihood that MCPs may require more connections to power up the various heat sources and measure the temperature of those heat sources. 3.1 Interface Connector The type and size of the interface connector is not critical for thermal measurements provided

16、 that the connector does not impinge on the buried planes and trace fan-out area defined by the above standards and does not render the board unusable in any of the thermal test environments described in JESD51. The interface connection should always occur on one board edge as shown in the reference

17、d documents; connectors are not allowed on any of the other three edges. Wires can be attached to the thermal test board but only in the area reserved for the edge-finger connector. No wires should be attached directly to package leads or contacts. The method for electrical interconnection to the bo

18、ard should be fully documented and included in the resultant data report generated for the thermal measurements. 3.2 Wire Routing Thermal test boards are designed to provide a well defined heat flow path from the mounted package into the board. For instance, JESD51-3 1 requires a minimum of 25mm-lon

19、g connection trace from the package body out to a plated through hole. The package and the trace areas constitute a “keep out” area no wiring may be in this area either on the top (package-mounted side) or bottom side of the board. The wiring implemented outside of the “keep out” area must not inter

20、fere with the thermal environment associated with a particular measurement. Some examples are: a) Forced Convection (i.e., moving air) measurements - the wiring should not interfere with normal air flow over the board and minimally perturb the air flow under the board. b) Junction-to-Board measureme

21、nts there is a second “keep out” area that has to be considered, the area where the ring cold plates clamp the board. This should not be a problem because the ring cold plates clamp on the board in the trace area. c) Natural Convection (i.e., still air) measurements - the wiring should not interfere

22、 with natural air flow over the board top surface. Thus, it is best to implement the wiring on the back side of the board. JEDEC Standard No. 51-32 Page 3 3.2 Wire Routing (contd) When adding additional wiring to a thermal test board, it is necessary to use wire of sufficient size (see Table 1 of 3)

23、 to handle the current requirements. As the voltage levels used in thermal measurements are usually relatively low, the wire insulation can be minimal. The wire routing implementation on the board should be fully documented and included in the resultant data report generated for the thermal measurem

24、ents. A top and bottom photograph of the board would be most helpful. 3.3 Board Traces and Planes The JESD51 series of board specifications 1-6 must be followed for the MCP packages for trace thickness, trace density to achieve the same conductivity of the board and connection to the package. Deviat

25、ions from the standard design that are required to supply the needed connections must always be designed to replicate the board conductivity of the original specification. The changes from the original specifications must be documented. JEDEC Standard No. 51-32 Page 4 STANDARD IMPROVEMENT FORM JEDEC

26、 JESD51-32 The purpose of this form is to provide the Technical Committees of JEDEC with input from the industry regarding usage of the subject standard. Individuals or companies are invited to submit comments to JEDEC. All comments will be collected and dispersed to the appropriate committee(s). If

27、 you can provide input, please complete this form and return to: JEDEC Attn: Publications Department 3103 North 10thStreet Suite 240 South Arlington, VA 22201-2107 Fax: 703.907.7583 1. I recommend changes to the following: Requirement, clause number Test method number Clause number The referenced clause number has proven to be: Unclear Too Rigid In Error Other 2. Recommendations for correction: 3. Other suggestions for document improvement: Submitted by Name: Phone: Company: E-mail: Address: City/State/Zip: Date: