1、JEDECSTANDARDTest Boards for Area Array SurfaceMount Package ThermalMeasurementsJESD51-9JULY 2000JEDEC SOLID STATE TECHNOLOGY ASSOCIATIONNOTICEJEDEC standards and publications contain material that has been prepared, reviewed, andapproved through the JEDEC Board of Directors level and subsequently r
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10、ll (703) 907-7559JEDEC Standard No. 51-9-i-TEST BOARDS FOR AREA ARRAY SURFACE MOUNTPACKAGE THERMAL MEASUREMENTSCONTENTSPageForeword i1 Scope 12 Normative references 13 Stock material 24 Board outline 35 Trace design 35.1 Top trace layer layout (both 1s and 2s2p PCBs) 35.2 Traces to thermal balls 45.
11、3 Trace widths for 1s and 2s2p PCBs 45.4 Ball lands for 1s and 2s2p PCBs 55.5 Thermal ball lands and thermal vias 55.6 Trace layers and connection routing 65.7 Buried layer layout (2s2p PCB only) 75.8 PCB metalization characteristics for 1s and 2s2p PCBs 75.9 Solder masks for 1s and 2s2p PCBs 75.10
12、Plated through-hole vias for 1s and 2s2p PCBs 86 Hand wiring 87 Data presentation 9Tables1 PCB sizes for packages 32 Drill diameters for thermal vias vs. ball pitch 63 PCB buried plane sizes 74 Wire size current limits 85 Specified parameters and values used 9Figures1a Cross section of 1s PCB showin
13、g trace and dielectric thicknesses in package placement 2and trace fan-out regions1b Cross section of 2s2p PCB showing trace and dielectric thicknesses 22 BGA test board outer dimensions and edge connector design 33 Traces to outer ball row flared to perimeter 25 mm from package body 34 Flared PCB l
14、ayout scheme 55 Package footprint routing 56 Nesting of 256 and 352 PBGA packages 77 Routing outside fan-out layer allowed in low conductivity PCB 78 Hand wiring test board suggestion 9JEDEC Standard No. 51-9-ii-ForewordPrevious thermal test board standards for leaded surface mount components have d
15、escribed the need for astandardized thermal test board design to allow comparison of thermal test results between organizations1-2. The present standard describes design standards for a test board that will allow no more than 15%measurement variability to occur between the minimum and maximum design
16、 parameters of thespecification. The standard is not intended to give actual in-use values, but rather a figure of merit foruse in comparing packages. Reference to the board used, 2s (1s effective) or 2s2p, must be made for allreported results.This specification is intended for use with the thermal
17、measurements and modeling specificationsgrouped under the JEDEC EIA/JESD51 series, 1. Specifically, the electrical test procedures describedin JEDEC EIA/JESD51-1, “Integrated Circuit Thermal Measurement Method - Electrical Test Method(Single Semiconductor Device),” 2, EIA/JESD51-2, “Integrated Circu
18、it Thermal Test MethodEnvironmental Conditions - Natural Convection (Still Air) ”, 3, and EIA/JESD51-6, “Integrated CircuitThermal Test Method Environmental Conditions - Forced Convection (Moving Air) ”, 4.JEDEC Standard No. 51-9Page 1TEST BOARDS FOR AREA ARRAY SURFACE MOUNTPACKAGE THERMAL MEASUREME
19、NTS(From JEDEC Board Ballot JCB-00-14, formulated under the cognizance of the JC-15.1 Subcommitteeon Thermal Characterization.)1 ScopeThis specification is meant to be broad enough to incorporate a wide variety of surface mount area arraypackage (e.g., BGA) design features and technologies. However,
20、 due to a limited number of signal layersthat results in shorting some device pins in this specification, the boards described here may not beadequate for measurement of active devices as compared to applications with thermal test chips.This specification covers surface mount area array packages int
21、ended to be mounted on a PCB. It doesnot cover area array packages that require sockets or PGA packages.2 Normative referencesThe following standards contain provisions that, through reference in this text, constitute provisions ofthis standard. At the time of publication, the editions indicated wer
22、e valid. All standards are subject torevision, and parties to agreements based on this standard are encouraged to investigate the possibility ofapplying the most recent editions of the standards indicated below.1 EIA/JESD51, Methodology for the Thermal Measurement of Component Packages (Single Semic
23、onductor Device).2 EIA/JESD51-1, Integrated Circuit Thermal Measurement Method - Electrical Test Method (Single Semiconductor Device).3 EIA/JESD51-2, Integrated Circuit Thermal Test Method Environmental Conditions -Natural Convection (Still Air).4 EIA/JESD51-6, Integrated Circuit Thermal Test Method
24、 Environmental Conditions -Forced Convection (Moving Air).5 Electronics Engineers Handbook, 3rd Edition, Edited by D.G. Fink and D. Christiansen,McGraw-Hill Book Co., NY, 1989, p 6.166 MIL-W-5088L, Amdt.1, Wiring, Areospace Vehicle.JEDEC Standard No. 51-9Page 23 Stock materialThe PCB test board shal
25、l be made of FR-4 material. The finish size shall be 1.60 mm +/- 10% thick. Forhigh ambient or board temperature applications ( 125 C), use of other test board material is acceptableas long as the thermal conductivity of the material is reported and measurement correlations have beenestablished betw
26、een the substitute material and FR-4.Trace thicknesses are achieved by starting with standard copper stock and then plating to finalthicknesses. A convention in PCB fabrication is to refer to copper thickness using the terminologyounces of copper per square foot of board. An ounce of copper per squa
27、re foot translates to a copperthickness of 35 m.The 1s test board has only a top trace layer in the component mounting and trace fan-out region (seefigure 1a). The copper trace thickness shall be 70 m (2 oz) +/- 20% for a ball pitch of 0.5 mm and 50m (1.5 oz) +/- 20% for a ball pitch 0.5 mm. A botto
28、m trace layer may be used for solder lands at theend of the fan-out traces and edge connection points. Connection to the edge connector outside thepackage fan-out region can be made with either the top or bottom signal traces. The 2s2p version of thistest board is formed by embedding two 35 m (1 oz)
29、 +0/-20% copper planes in the PCB (as shown infigure 1b), while maintaining the finish thickness at 1.60 mm.Figure 1a Cross section of 1s PCB showing trace and dielectric thicknesses in packageplacement and trace fan-out regionsFigure 1b Cross section of 2s2p PCB showing trace and dielectric thickne
30、sses1.60 mmComponent Trace, 2 oz *Plane 1, 1 oz, solidPlane 2, 1 oz, solidBackside Trace, 2 oz *AA0.25 mm A 0.5 mm* = finish thickness:1 oz/ft2= 35 m2 oz/ft2= 70 m1.60 mmComponent Trace, 2 oz * = finish thickness:2 oz/ft2= 70 mJEDEC Standard No. 51-9Page 34 Board outlineThe board shall be 101.5 mm x
31、 114.5 mm +/- 0.25 mm in size for packages less than or equal to 40 mmon a side (see figure 2). A typical edge connector is depicted in figure 2. The edge connector can be pin-out and pitch modified for specific needs. Modification of the width dimension of the edge connector isallowed. Multiple row
32、s of vias along the edge connector are allowed.For various package sizes, refer to table 1 for the appropriate PCB size.Table 1 PCB sizes for packagesPackage Length PCB Size (+/- 0.25 mm)Pkg. Length 40 mm 101.5 mm x 114.5 mm (4.0 in x 4.5in)40 mm 0.5 mm. For pitches 0.5 mm., the total finished trace
33、 width shall be 45% to 55% of the solder ball pitch. Achieving thefinish size may require some oversize in design to compensate for over-etching of the copper tracesduring processing. Traces shall terminate in a plated through-hole for soldering interconnect purposes.See 5.10 for a description of th
34、e plated through-hole vias.JEDEC Standard No. 51-9Page 75 Trace design (contd)ThermalBall LandFigure 5 Package footprint routingExamples:a) Routing a corner of an array - arrows highlight a trace broken to eliminate a VHIto VLOshortb) Routing a staggered arrayc) Routing with a diagonal corner traced
35、) Full array routing schematice) Routing to thermal balls (open circles) at center of package (1s only)f) Routing to thermal balls using diagonal connections (1s only)g) 2 traces per ball position routing options. Total trace width to be 40% of ball pitch for each ball position. Top ofdiagram shows
36、connection of every other ball. Side of diagram shows connection of every other ball pair. Centerconnection to thermal balls for 1s design only.h) No connection allowed to thermal balls on 2s2p designJEDEC Standard No. 51-9Page 85 Trace design (contd)5.4 Ball lands for 1s and 2s2p PCBsBall lands sho
37、uld be sized according to the technology in use for the solder balls. Solder masking must beused to avoid solder wicking from the ball into through-hole vias on the thermal test board or ontoelectrical interconnect traces.5.5 Thermal ball lands and thermal vias1s PCB: Thermal vias in the 1s PCB are
38、not allowed.2s2p PCB: All center thermal balls on the package shall connect to the top buried copper plane throughthermal vias on the test PCB. This plane may be either the buried VHIor VLO. The thermal vias shallhave drill diameters as specified in table 2 as a function of the ball pitch of the pac
39、kage and shall beplated to 18 m copper minimum thickness throughout the via barrel. A cross pattern on the connectedplane shall not be used; the connected plane shall remain unetched in the vicinity of the drill hole. Whenisolating a thermal via from a buried plane, use an isolation clearance diamet
40、er no less than 0.20 mmgreater than the hole diameter. The isolation clearance regions for adjacent thermal vias shall not merge,making the buried plane discontinuous. The thermal via must be offset from the ball land to avoidwicking the solder ball into the via during solder reflow.Table 2 Drill di
41、ameters for thermal vias vs. ball pitchBall pitch Thermal via outer diameter (O.D.)1.50 mm 0.40 mm +/- 10%1.27 mm 0.35 mm +/- 10%1.00 mm 0.30 mm +/- 10%0.75 mm 0.80 mm 0.25 mm +/- 10%0.65 mm 0.20 mm +/- 10%0.50 mm 0.20 mm +/- 10%To allow for nesting of different packages on the same PCB design, the
42、thermal ball lands may bearrayed to match the largest thermal ball array of the packages to be tested on the PCB. If a thermal ballland and via pair in such an array are actually being used by a signal I/O, the connection between thethermal ball land and via may be cut or trimmed without violating t
43、his specification. Such trimmingshould remove as much of the connecting trace as possible.JEDEC Standard No. 51-9Page 95 Trace design (contd)5.6 Trace layers and connection routing1s PCB: The only pattern permitted within the flared perimeter (fan-out area) is the fan-out pattern andpackage footprin
44、t on the top trace layer. The bottom layer shall be used only for via termination andlimited connection routing to the edge connector. Routing to the edge connector is allowed in either thetop or bottom signal layers if the interconnection remains outside the flared perimeter of the throughholes (se
45、e figure 7). No traces, except as noted below, are allowed to run under the PCB within theflared perimeter of the through holes. Power connection routing should be designed to minimize voltagedrops and self-heating across the PCB traces. Measurement force (power) and sense (measure) linesshould be k
46、ept independent of each other from the edge connector to the package terminals.2s2p PCB: The top trace layer shall be used for fan-out and interconnection to the edge connector outsidethe fan-out perimeter. Any required interconnection routing to the edge connector can be made using thebottom trace
47、layer and the top layer as long as the top layer interconnection remains outside the packagefan-out region. Power connection routing should be designed to minimize voltage drops and self-heatingacross the PCB traces. Measurement force (power) and sense (measure) lines should be keptindependent of ea
48、ch other from the edge connector to the package terminals. Vias between “signaltraces” and the buried planes are allowed for power and ground connections only and must be outside ofthe fan-out traces.1s and 2s2p PCB: To route a signal from the interior of a large array to the edge connector, it may
49、benecessary to use a via adjacent to the signal ball and a trace on the backside of the PWB. This isacceptable if the total width of traces, both topside and backside, connected to balls of the same row,does not exceed the total specified in 5.3. The via, via pad and isolation clearance shall be sized inaccordance with 5.5. The via must be isolated from any internal copper planes. The trace shall be routeddirectly beneath the topside traces for the balls of the same row until outside the fan-out region.Figure 6 Nesting of 256 and 352
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