JEDEC JESD54-1996 Standard for Description of 54 74ABTXXX and 74BCXXX TTL-Compatibility BiCMOS Logic Devices《54 74ABTXXX和74BCXXX TTL兼容 BiCMOS逻辑设备描述规范》.pdf

1、EIA JESD54 96 I 3234600 0567647 255 EIMJEDEC STANDARD _ _ Standard for Description of 54174ABTXXX and 74BCXXX TTL-Compatibility BiCMOS Logic Devices EIAiJESD54 FEBRUARY 1996 ELECTRONIC INDUSTRIES ASSOCIATION ENGINEERING DEPARTMENT EIA JESD54 96 I 3234600 0567648 191 I NOTICE EWJEDEC Stanbds and Publ

2、ications contain matenal that has been prepared, progressively reviewed, and approved through the JEDEC Council level ad subsequently reviewed and approved by the EIA General Counsel. EINJEDEC Standards and Publications are designed to serve the public inkrest through eliminating misunderstanings be

3、tween manufacturers and purchases, facilitating interchangeability and improvement of products, and assisting the purchaser is selecting and obtaining with minimum delay the proper product for his particular need. Existence of such standards shall not in any respect preclude any member or nonmember

4、of JEDEC from manufacturing or selling products not confonnllig to such standards, nor shall the existence of such standards preclude their voluntaxy use by those other than EIA members, whether the standard is to be used either domesticaiiy or intimationally. EINJEDEC Standards and Publications are

5、 adopted without regard to whether their adoption may involve patents or articles, materials, or processes. By such action, EWJEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the EWJEDEC Standards or Publications. The information

6、 included in EWJEDEC Standards and Publications represents a sound approach to product specification and application, principally fiom the solid state device manufacturer viewpoint. Within the EINJEDEC organization there are procedures whereby an EWJEDEC Standard or Publication may be further proces

7、sed and ultimately becomes an ANSEIA Standard. Inquiries, comments, and suggestions relative to the content of this EWJEDEC Standard or Publication should be addressed to the JEDEC Executive Secreary at EIA Headquarters, 2500 Wilson Boulevard, Arlington, VA 2220 1. Published by QELECTRONIC INDUSTRIE

8、S ASSOCIATION 1996 2500 Wilson Boulevard Arlington, VA 2220 1 EngineeringDepartment “Copyright” does not apply to JEDEC member companies as they are fiee to duplicate this document in accordance with the latest revision of the JEDEC Publication 21 “Manual of Organization and ProCsdure”. PRICE: Pleas

9、e refer to the current Catalog of EIA, JEDEC, and TIA STANDARDS and ENGINEERING PUBLICATIONS or call Global Engineering Documents, USA and Canada (1-8OO-854-7179) International (303-397-7956) Printed in U.S.A. Ali rights reserved EIA JESD54 96 3234600 0567649 O28 PLEASE! DONT VIOLATE THE LAW! This d

10、ocument is copyrighted by the EIA and may not be reproduced without permission. Organizations may obtain permission to reproduce a limited number of copies through entering into a license agreement. For information, contact: Global Engineering Documents 15 Inverness Way East Englewood, CO 80 1 12-57

11、04 or call U.S.A. and Canada 1-800-854-71 79, International (303) 397-7956 EIA JESD54 b 3234600 0567650 84T EIAIJEDEC Standard No. 54 Standard for Description of 54/74ABTXXX and 74BCXXX TTLCompatible BiCMOS Logic Devices (From JEDEC Council ballot JCB-95-67, formulated under the cognizance of JC-40

12、Committee on Standardization of Digital Logic.) CONTENTS Section 1 PURPOSE AND SCOPE 1.1 Purpose 1.2 Scope 2 DEFINITIONS 3 STANDARD SPECIFICATIONS 3.1 Absolute Maximum Continuous Ratings 3.2 Recommended Operating Conditions 3.3 ABT DC Specifications 3.4 BC DC Specifications 4 TEST CIRCUITS AND SWITC

13、HING WAVEFORMS 5 SUPPLY CURRENT TEST PROCEDURES 6 ABT SWITCHING SPEED STANDARDS 6.1 Index of Device Types 6.2 Switching Speed Tables 7 BC SWITCHING SPEED STANDARDS 7.1 index of Device Types 7.2 Switching Speed Tables -1- Page 1 5 12 13 13 14 29 29 30 EIA JESD54 96 3234600 0567653 786 m EIMJEDEC Stan

14、dard No. 54 Page 1 1 PURPOSE AND SCOPE 1.1 Purpose: To provide a standard of BiCMOS Logic series specifications to provide for iniformity, multiplicity of sources, elimination of confusion, and ease of device specification and design by users. 1.2 Scope: This standard covers specifications for BiCMO

15、S Logic series as defined in Section 2. 2 DEFINITIONS BiCMOS Series Includes devices combining bipolar and silicon-gate complementary metal-oxide-semiconductor (CMOS) field effect devices in a single-chip integrated circuit. ABTXXXXXX Series Includes devices whose input logic levels are TTL compatib

16、le, whose outputs are specified at lTL levels. BCXXX Series Includes devices whose input logic levels are lTL compatible, whose outputs are specified at lTL levels and the output sink current is specified at either 24mA or 48mA. Pref ixes Prefixes “54“ or “74“ immediately preceding “ABT or “BC“ indi

17、cate the operating temperature range. For example, 54ABTXXXXXX refers to the Military (MIL) version of devices which are specified over the temperature range of -55C to 125C. 74BCXXX or 74ABTXXXXXX refers to the Commercial (COML) version of devices which are specified over the temperature range of -

18、40C to 85C. EIA JESD54 96 3234600 0567652 bL2 Symbol vcc VI EIAIJEDEC Standard No. 54 Page 2 Parameter MIN NOM MAX Unit Supply voltage 4.5 5 5.5 v Input Voltage O vcc v 3 STANDARD SPECIFICATIONS 3.1 Supply Voltage, VCC -0.5 V to 7 V dc input voltage, VI (Note 3) . 4.5 V to VCC dc output voltage, Vo

19、-0.5 V to 5.5 V dc input clamp current, IIK (VI O) . -1 8 mA dc output clamp current, lo (VO O) -30 mA dc current into any output in the low state, lo (Note 4) 2 x lOL(rated) dc current into any output in the high state, lo (Note 5) 2 x loH(rated) Storage temperature range -65C to 150C Absolute Maxi

20、mum Continuous Ratings (Notes 1 and 2): . I I Vo I Output voltage 10 I Ivcc IV I I TA I Operating free-air temperature I I- 54 Series 1-55 125 1125 lC I 1 I I I I I AUAv I Input transition rise or fall rate (Note 1) O 5 nsN I Note 1 : As measured between 0.8 V and 2 V. EIA JESD54 96 3234600 0567653

21、559 = I I I I 2.5 mA VI = VCC - 2.1 V or VI = 0.5 V, , Vcc = MIN to MAX 3.3 ABT dc Specifications: MIN 2 Symbol VIH VIL VIK VOH VOL II IIH IIL IOZH IOZL los Iccz ICCH ICCL AICC MAX V Parameter High-ievel input voltage OH = -3 mA IOH = -12 mA lo = -24 mA, (Note 5) Vcc = MIN, VI = VIH or VIL Low-level

22、 input voltage 2.4 V 2 V 2 V Input clamp voltage IOH = -32 mA, (Notes 4.5) IOL = 12 mA High-ievel output voltage 2 V 0.8 V Low-level output voltage Vcc = MIN, VI = VIH or VIL Input current 1 0.55 V loL = 48 mA, (Note 5) loL = 64 mA, (Notes 4,5) 0.55 V High-ievel input current Vcc = MAX, VI = vcc Low

23、-level input current except 110 ports 0.1 mA I/O ports 1 mA Off-state output current (Note 1) Vcc = MAX, Vcc = MAX, except I/O ports Il0 ports except I/O ports I/O ports Vo = 2.7 V Vo = 0.5 V Off-state output current (Note 1) 50 PA 60 PA -50 PA -60 PA Output short-circuit current (Note 2) (Note 3) V

24、cc = MAX, VI = VCC or GND Static supply current, outputs high-impedance pA Static supply current, outputs high Static supply current outputs low Static supply current per inDut at lTL levels EINEDEC Standard No. 54 Page 3 54/74 Series Test Conditions Unit Vcc = MIN, II =-18 rnA I (-1.2 IV Vcc = MAX,

25、 VI = 2.7 V I 110 I Vcc = MAX, VI = 0.5 V Vcc = MAX, vo=o 1-50 I I mA Vcc = MAX, VI = VCC or GND Vcc = MAX, VI = VCc or GND Note 1: For I/O pins, IOZH and IOZL include the input leakage current. Note 2: Not more than one output should be shorted at a time, and the duration of the short circuit shoul

26、d not exceed one second. Note 3: Refer to manufacturers datasheets. Note 4: Not applicable to 54 series products. Note 5: Not applicable to series resistor parts. EIA JESD54 96 3234600 O567654 475 H VIH Vi, EIVEDEC Standard No. 54 Page 4 High-level input voltage 2 V Low-level inout voltaae 0.8 V 3.4

27、 BC dc Specifications: VIK Input clamp voltage Symbol I Parameter -1.2 V Vcc = MIN, II = -18 mA I Test Conditions VOH MIN IMAX I “It I IOH = -3 mA 2.4 V VI = VIH or VIL lo=-l5mA 2 V Vcc = MIN, High-level output voltage VOL Vcc = MIN, loL = 24 mA 0.55 V VI = VIH or VIL IOL = 48 mA (Note 3) V Low-ieve

28、l output voltage II Vcc = MAX, except I10 ports 1 PA vi = vcc I/O ports 1 mA Input current IIH J Vcc = MAX, except I10 ports 1 PA Il0 ports 50 PA High-level input current Vi = 2.7 V IIL Vcc = MAX, except 110 ports -1 PA Vi = 0.5 V I/O ports -50 PA Low-level input current 50 Off-state output current

29、Vcc = MAX, IOZH (Note II Vn = 2.7 V Vcc = MAX, ICCH I outDuts hiah I Vi = VCC or GND Static supply current, PA I Po IPA I IOU los ICcz - -50 PA -60 mA Off-state output current (Note 2) Output short-circuit current Vcc = MAX, Vo = 0.5 V Vcc = MAX, (Note 2) vo=o 50 PA Static supply current, Vcc = MAX,

30、 outputs highimpedance VI = VCC or GND i ICCL CC Static supply current vcc = MAX, (Note3) mA outputs low Static supply current per 1.5 mA Vi = VCC or GND VI = VCC - 2.1 V or VI = 0.5 V, input at TTL levels Vcc = MIN to MAX EIA JESD54 b m 3234600 05b7b55 321 Generator EINJEDEC Standard No. 54 Page 5

31、= CL 4 TEST CIRCUITS AND SWITCHING WAVEFORMS Test tpLH (except open-collector outputs) Switch Open tpHL (except open-collector outputs) tpHL (open-collector outputs) tPZH tPZL tPHZ I fPLH (open-coiiector outputs) I 7v I Open 7v Open 7v Open I tPlZ I 7v 1 7v OPEN CL = 50 pF or equivalent (includes ji

32、g and probe capacitance) RL = R1 = 500 R or equivalent RT = FIL = 500 Q CL = 50 pF tr = tf = 2.5 ns (or as fast as required) from 10% to 90% of O V to 3 V. EIA JESD54 96 II 3234600 0567b57 LT4 EINJEDEC Standard No. 54 Page 7 SETUP AND HOLD TIME MEASUREMENTS 3v Data Input 1.5V ov I l I -t,* tsu - ENA

33、BLE TIME MEASUREMENTS Enable Input output High-Z to Low output LOW-2 to High EIA JESD54 96 I 3234600 0567658 030 EINJEDEC Standard No. 54 Page 8 DISABLE TIME MEASUREMENTS 3v Y, - Enable Input - ; - ov I I I EIA JESD54 96 3234600 0567659 T77 EINJEDEC Standard No. 54 Page 9 5 SUPPLY CURRENT TEST PROCE

34、DURES This section contains the test measurement procedure and test conditions to be used when measuring ICCL on BiCMOS logic devices. A description of the symbols used follows the table. Refer to Sections 3.3 and 3.4 for other ICC measurement parameters. _ Note: The above symbols are interpreted as

35、 follows: H = Vcc L = GND (O V) M = Force VCC Measure ICC 3v - C=Clockpulse J7, GND X = Dont care; VCC or GND, but not switching G = GND (O V) O = Open EIA JESD54 96 E 3234600 0567660 799 Devic - 646 - 648 - 651 - 652 657 821 823 827 833 841 843 853 861 - - - 863 899 2952 - 2953 EINJEDEC Standard No

36、. 54 Page 10 03 HL HH HH HL LL O0 LL LL LL LL O0 LL LL LL O0 LL O0 LL O0 HL O0 LL O0 HH I I Pin Number I O4 LO LO LO LO LO 05 O0 HH O0 HH O0 LL O0 LL O0 LL LL LL LL O0 LL LL LL O0 LL O0 LL O0 LL O0 O0 LL O0 HH - A to B B to A AtoB O6 LL B to A AtoB B to A O0 HH O0 HH O0 LL O0 ML MO LL LL LL LL O0 LL

37、 LL LL O0 LL O0 LL O0 LL O0 O0 LL O0 HH AtoB H L BtoA L O LL LL o708 LL LL AtoB H L BtoA L O B to A Note: The above symbols are interpreted as follows: H = Vcc L = GND (O V) M = Force VCC Measure ICC 3v - C=Clockpulse n - - GND X = Dont care; VcC or GND, but not switching G = GND (O V) O = Open 11 1

38、2 13 14 I5 16 17 I6 19 L 1G 10 lOlOlOlOlOl0 OGLLLLL L L # HG0000000 I1II1ILI L IG IL ICIL lolololo IIIIIIII 20 21 22 23 24 25 26 27 26 IoILIxIxIMI I I I HLLXM # OHXXM 0000M 0000M 0000M LLLLM LLLLM O 010 O O O O L M LLLLLLLHM LLLLM 0000M LIII1III EIA JESD54 b m 3234b00 05b7bbL 625 m EINJEDEC Standard

39、 No. 54 Page 11 I Pin Number I I EIA JESD54 96 111 3234600 0567662 561 23 51 O0 O0 O0 LL LL O0 O0 LL O0 O0 LL EINJEDEC Standard No. 54 Page 12 24 52 LL O0 LL LL LL I I Pin Number 1 11 39 GL GO GO GL GL GO GO GL GL GO GO GL GL GO GO GL - Device 12 40 16543 - 16646 - 16652 - 17 45 OG OG OG OG OG OG OG

40、 OG 16952 - 18 46 LG LG LG LG LG LG LG LG A to B 21 40 OM OM OM OM OM B to A - A to B B to A - AtoB 22 50 LM OM OM LM LM LM LM LM LM OM LM B to A 0304 31 I XG XG XG A to B 32 LG LG LG LG LG LG LG LG LG LG LG LG LG 9 to A - 105 33 LL lo L IL O0 O0 O0 LL LL O0 O0 LL LL O0 O0 LL O6 34 O L I07 , 35 1M i

41、M IM M 1 MO MO MO ML ML MO O0 i 1M ML MO IM ML O8 36 L O L L L O o1 29 HL HL HX HX HX HX HX 02 30 LL LL HX LX LX LX LX LC LC Note: The above symbols are interpreted as follows: H = Vcc L = GND (O V) M = Force VCC Measure icc 3v - c=clkpulse n - - GND X = Dont care; VCC or GND, but not switching G =

42、GND (O V) O = Open o9 3738 10 I O0 L O0 O0 LL LL O0 O0 LL LL O0 O0 LL 10 LL o LL L 5 O0 I O0 O0 LL O0 O0 LL LL O0 O0 LL LL O0 O0 LL 1 LL O0 f EIA JESD54 96 111 3234600 0567663 4T EINJEDEC Standard No. 54 Page 13 6 ABT SWITCHING SPEED STANDARDS This section establishes standard maximum limits for swi

43、tching parameters and minimum limits for timing parameters for the device types listed herein. For parameter measurement information, refer to Section 4. Refer to individual manufacturers datasheets for applicable minimum limits for switching parameters. Standardized limits for switching parameters

44、(dynamic characteristics) are specified by part identifiers in numeric order. 6.1 Index of ABT device types: 6.1.1 Buffers and Drivers: 125,126,240,2240(240-l), 241,244,2244(244-l), 540,541,827,16244, 16540,16541 6.1.2 Latches and Flip-Flops: 6.1.3 Transceivers: 273,373,374,377,533,534,573,574,821,8

45、23,841,843, 16373, 16374 245, 620,623,640,861,863,16245 6.1.4 Registered Transceivers: 6.1.5 Transceivers with Parity: 543,544,646,648,651,652,2952,2953,16500,16501,16543,16646,16652,16952 657,833,853,899 EINJEDEC Standard No. 54 Page 14 6.2 ABT Switching speed tables: 6.2.1 Buffers and Drivers: EIA

46、 JESD.54 96 3234600 0567665 270 m 827 16244 16540 16541 EINJEDEC Standard No. 54 Page 15 tPHZ Maximum output disable delay, G to Y 8.8 ns tPL2 PLH Maximum propagation delay, A to Y 4.8 ns PHL Maximum output enable delay, G to Y 8.6 ns tPHZ Maximum output disable delay, F to Y 7.2 ns tPLZ Maximum pro

47、pagation delay, A to Y 4.1 ns PLH PHL $;: Maximum output enable delay, G to Y 6.3 ns Maximum output disable delay, G to Y 6.7 ns tPLZ PLH Maximum propagation delay, A to Y 4.3 ns PHL t: Maximum output enable delay, G to Y 5.9 ns tPHZ Maximum output disable delay, G to Y 5.3 ns tPLZ PLH Maximum propa

48、gation delay, A to Y 4.2 ns PHL Maximum output enable delay, G to Y 6 ns 1PHZ Maximum output disable delay, to Y 5.1 ns tPU tPHZ EIA JESD54 96 m 3234600 0567666 LO7 m tPLH PHL tpHL EINJEDEC Standard No. 54 Page 16 Maximum propagation delay, CLK to Q 7.3 ns Maximum propagation delay, to Q 7.4 ns I D

49、before CLK? 2.5 ns 6.2.2 Latches and Flip-Flops: tsu h 1, Symbol I Parameter 174 series I 54 Series I Units D before CLK? 2 ns CIKEN before CLK? 3 ns D ater CLK? 1.8 ns CIKEN after CLK? 1.8 ns Minimum hold time Minimum Dulse duration, CLK high or low 3.3 ns Minimum setup time ? PHL trem Minimum removal time I - D to U 6.6 ns LE to 0 7.3 ns Maximum propagation delay I I I 2 ns I CIX inactive before CLKT ?PZH I Maximum output enable delay, G to Q 6.7 tP71 Maximum propagatio