1、EIA/JEDECSTANDARDI/O Drivers and Receivers withConfigurable Communication Voltage,Impedance, and Receiver ThresholdJESD67FEBRUARY 1999ELECTRONIC INDUSTRIES ALLIANCEJEDEC Solid State Technology AssociationElec:tlllnic: Industries AllianceNOTICEEIA/JEDEC standards and publications contain material tha
2、t has been prepared, reviewed, andapproved through the JEDEC Board of Directors level and subsequently reviewed and approvedby the EIA General Counsel.EIAiJEDEC standards and publications are designed to serve the public interest througheliminating misunderstandings between manufacturers and purchas
3、ers, facilitatinginterchangeability and improvement of products, and assisting the purchaser in selecting andobtaining with minimum delay the proper product for use by those other than JEDEC members,whether the standard is to be used either domestically or internationally.EWJEDEC standards and publi
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5、e information included in EIAIJEDEC standards and publications represents a sound approachto product specification and application, principally from the solid state device manufacturerviewpoint. Within the JEDEC organization there are procedures whereby an EIAIJEDECstandard or publication may be fur
6、ther processed and ultimately become an ANSllEIA standard.No claims to be in conformance with this standard may be made unless all requirements stated inthe standard are met.Inquiries, comments, and suggestions relative to the content of this EIAiJEDEC standard orpublication should be addressed to J
7、EDEC Solid State Technology Association, 2500 WilsonBoulevard, Arlington, VA 22201-3834, (703)907-7560/7559 or www.jedec.org.Published byELECTRONIC INDUSTRIES ALLIANCE 1999Engineering Department2500 Wilson BoulevardArlington, VA 22201-3834“Copyright“ does not apply to JEDEC member companies as they
8、arefree to duplicate this document in accordance with the latest revision ofJEDEC Publication 21 “Manual ofOrganization and Procedure“.PRICE: Please refer to the currentCatalog ofJEDEC Engineering Standards and Publications or call Global EngineeringDocuments, USA and Canada (1-800-854-7179), Intern
9、ational (303-397-7956)Printed in the U.S.A.All rights reservedJEDEC Standard No. 671/0 DRIVERS AND RECEIVERS WITH CONFIGURABLE COMMUNICATIONVOLTAGE, IMPEDANCE, AND RECEIVER THRESHOLDContentsPageForeword1 Flexible I/O interface supply voltage: I1.1 Nominal supply voltages and I/O parametrics1.2 Inter
10、operability2 Flexible I/O interface supply voltage: II2.1 Nominal supply voltages and 1/0 parametrics2.2 Interoperability3 Flexible liD interface receiver3.1 Receiver types3.2 Interoperability4 Flexible I/O interface driver impedance4.1 Impedance specification4.2 Impedance selectionTables1-1 Expecte
11、d migration ofsupply voltages and receiver reference voltage1-2 Nominal interface parametrics1-3 Relationship between VDD, VDDQ, and Vref2-1 Expected migration ofsupply voltages and receiver reference voltage2-2 Nominal interface parametrics2-3 Relationship between VDD, VDDQ, and Vref-iiI12334555666
12、122344JEDEC Standard No. 67ForewordThis standard attempts to aid the design of electronic Systems comprised of components thatoperate at several different supply voltages. This standard is developed around the followingprinciples:If two or more chips of different voltages are in communication, the c
13、ommunication voltageshoUld be equal to the lowest supply voltage. Thus drivers and receivers should beconfigurable in their communication age.The reference or switch point of the receiver should track with the communication voltage.The reference may be either externally or internally supplied. Thus
14、receiver mode should beconfigurable.The impedance of the driving circuits should be matched to the load, independent of thecommunication voltage. Thus the driving circuit impedance should be configurable.IntroductionThis standard is the compilation of 4 separate JEDEC documents covering respectively
15、configurable I/O voltage, receiver type and switchpoint, and driver impedance.The intent of sections I and 2 is to guide designs ofinterface driver and receiver circuits to allowcommunication between chips of different supply voltages VDD. Although the communicationvoltage VDDQ may exceed the supply
16、 voltage, this standard is intended to guide designs ofinterface circuits that operate with VDDQ at or less than VDD. The use ofcircuits which operateat more than one well defmed interface voltage will allow communication between chips ofdifferent supply voltages with a minimum effect on I/O delay,
17、speed, reliability, or chip area.These sections cover power supply voltages VDD from 3.3V to 1.8Vand 1.5V to O.8V.The intent of section 3 is to guide designs of interface receiver circuits to allow operation withmore than one method of defining the receiver switch point or reference voltage. As circ
18、uitspeeds increase and circuit operating voltages decrease, different circuit techniques may beemployed. Broadly described, the techniques can be separated into two types: those circuits thatuse an external voltage reference to define a switch point, and those circuits that use an internalreference,
19、 contained wholly within the chip, to define a receiver switch point. This section coversboth types ofreceivers and describes how to switch from one type to the other. It is expected thatthe switch from externally referenced receivers to internally referenced receivers will in generalresult in some
20、loss ofcommon mode noise rejection.-11-JEDEC Standard No. 67Introduction (contd)The intent of section 4 is to improve the specification of semiconductor off-chip driver circuits.The improved specification will allow a better match of circuit driver performance and outputload. In addition the section
21、 allows for selectable driver strength,. thus allowing a semiconductordevice to operate optimally under different output loading conditions. In particular, thisspecification will refer to the value of a driver circuit output impedance, and is intended formatching to the impedance of transmission lin
22、e structures for high speed communicationbetween semiconductor devices.-111-JEDEC Standard No. 67Page 1I/O DRIVERS AND RECEIVERS WITH CONFIGURABLE COMMUNICATIONVOLTAGE, IMPEDANCE, AND RECEIVER THRESHOLD(From Council Ballots JCB-97-59, JCB-97-60, JCB-97-61, and JCB-97-62, fonnulated under thecognizan
23、ce ofthe JC-16 Committee on Electrical Interface and Power Supply Standards forElectronic Components.)1 Flexible I/O interface supply voltage: I1.1 Nominal supply voltages and I/O parametricsThe supply voltage of semiconductors is expected to decrease to below one volt over the nextseveral years. As
24、 a result, it is expected that systems will be developed utilizing semiconductorchips ofdifferent supply voltages. Table 1-1 below shows how we expect the supply voltage, andhence the maximum communication voltage, to migrate.ence voltagedItfd- xpecte mle;ratlOn 0 supply vo ae;es an receIver re erVD
25、D,VDDQ (Volts) 3.3 2.5 1.8 1.5Vref(Volts) 1.5 1.25 0.9 0.75Table 1-1 EThe relationship is approximately Vref= VDDQ/2.To facilitate communication between chips of different supply voltages, we have specified theinterface parametrics. They are separated into a High Perfonnance Class (Class A) and a Wi
26、deMargin Class (Class B). The high perfonnance interface specifications are primarily intended forhigh speed communication where sensitive receivers, perhaps based on externally referenceddifferential amplifiers, and are used to reduce the cycle time at the expense of power. The widemargin interface
27、 specifications are intended primarily for slower speed communication wherepower is reduced and where less sensitive, more noise tolerant receivers can he used, perhapsbased on internally referenced circuits. The voltage of an entry, Vih or Vil, in table 2 is(calculated by using the nominal values o
28、fVDD and VDDQ ofthe receiver. The voltage, Vih orViI, when expressed in volts, is valid to 2 decimal places (+/- lOmV). The Vih and ViI oftable 1-2 are expected to hold for all operating conditions.JEOEC Standard No. 67Page 21.1 Nominal supply voltages and I/O parametrics (contd)Table 1-2 - Nominal
29、Interface ParametricsClass A (High Performance) Class B (Wide Margin)Vih(DCLmin = Vref + 0.07 * VDO Vih(OCLmin = Vref + 0.14 * VOOVih(DCLmax = VODQ + 0.10 * VDO Vih(DC) max = VDOQ + 0.10 * VODVil(DC)_max = Vref - 0.07 * VDO Vil(DCLmax = Vref-0.14 * VODVil(OCLmin = VSS Vil(OCLmin = VSSVih(ACLmin = Vr
30、ef + 0.14 * VDO Vih(ACLmin = Vref + 0.25 * VODVih(ACLmax = VOOQ + 0.15 * VDD Vih(ACLmax = VOOQ + 0.15 * VODVil(ACLmax = Vref-0.14 * VDO Vil(ACLmax = Vref - 0.25 * VDDVil(ACLmin = VSS - 0.15 *VDO Vil(ACLmin = VSS - 0.15 * VDDAlthough it is commonplace to standardize Output driver current and output d
31、river voltages(Voh, Vol), this standard will refer to output driver impedances. Through reference to driverimpedance the driver characteristics will become easier to define and the resultant driverbehavior under various loading conditions will be easier to predict. For the expected values fordriver
32、impedance and the parametrics associated with the drivers (see section 4).1.2 InteroperabilityIt is expected that a group ofdevices of different supply voltages VOD will communicate with acommon communication voltage VDOQ which is equal to or less than VOO_low the lowestsupply voltage of the group.
33、Although it is desirable that chips of supply voltage VDD operateover the largest possible range ofVDDQ, to meet this standard it is sufficient that chips ofVDDspecified in table 1-3 support communication at the associated values of VOOQ, with the ViI,Vih specifications oftable 1-2.Table 1-3 - Relat
34、ionship between VDD, VDDQ, and VrefVDD VDDQ Vref3.3V 3.3V,2.5V 1.5 V, 1.25V2.5V 2.5V, 1.8V 1.25V, 0.9V1.8V 1.8V, 1.5V, 1.2V 0.9V, 0.75V, 0.6VThe relationship is roughly VDO:S; VDDQ :s; 0.6 x VDOJEDEC Standard No. 67Page 31.2 Interoperability (contd)Similarly the I/O drivers associated with a semicon
35、ductor device operating with external voltageVDD must be capable ofproviding an output voltage satisfying the input requirements ViI andVih oftable 1-2 for a receiver configured for any associated VDDQ in table 1-3, at the specifiedimpedance. Separate VDDQ pins are recommended but not required. Sepa
36、rate VSS and VSSQpins are acceptable but not required.2 Flexible 1/0 interface supply voltage: II2.1 Nominal supply voltages and 110 parametricsThe supply voltage of semiconductors is expected to decrease to below one volt over the nextseveral years. As a result, it is expected that systems will be
37、developed utilizing semiconductorchips ofdifferent supply voltages. Table 2-1 below shows how we expect the supply voltage, andhence the maximum communication voltage, to migrate.ence voltagedItft d- xpec e ml2ratIOn 0 supply vo a2es an receIver re erVDD,VDDQ (Volts) 1.5 1.2 1.0 0.8Vref(Volts) 0.75
38、0.6 0.5 0.4Table 2-1 EThe relationship is approximately Vref= VDDQ/2.To facilitate communication between chips of different supply voltages, we have specified theinterface parametrics. They are separated into a High Performance Class (Class A) and a WideMargin Class (Class B). The high performance i
39、nterface specifications are primarily intended forhigh speed communication where sensitive receivers, perhaps based on externally referenceddifferential amplifiers, and are used to reduce the cycle time at the expense of power. The widemargin interface specifications are intended primarily for slowe
40、r speed communication wherepower is reduced and where less sensitive, more noise tolerant receivers can be used, perhapsbased on internally referenced circuits. The voltage of an entry, Vih or Vii, in table 2-2 iscalculated by using the nominal values of VDD and VDDQ of the receiver. The voltage, Vi
41、h orViI, when expressed in volts, is valid to 2 decimal places (+/- 10mV). The Vih and ViI oftable 2-2 are expected to hold for all operating conditions.JEDEC Standard No. 67Page 42.1 Nominal supply voltages and 1/0 parametrics (contd)Nominal Interface ParametricsClass A (High Performance) Class B (
42、Wide Margin)Vih(DCLmin = Vref + 0.07 * VDD Vih(DCLmin=Vref + 0.14 * VDDVih(DCLmax = VDDQ + 0.10 * VDD Vih(DCLmax= VDDQ+ 0.10 * VDDVil(DCLmax = Vref - 0.07 * VDD Vil(DCLmax = Vref - 0.14 * VDDVil(DCLmin = YSS Vil(DCLmin=VSSVih(ACLmin = Vref + 0.14 * VDD Vih(ACLmin=Vref + 0.25 * VDDVih(ACLmax = VDDQ +
43、 0.15 * VDD Vih(ACLmax=VDDQ + 0.15 * VDDVil(AC) max = Vref- 0.14 * VDDVil(ACLmax= Vref- 0.25 * VDDVil(AC) min = VSS-0.15 *YDD Vil(ACLmin = VSS - 0.15 * VDDAlthough it is commonplace to standardize output driver currents and output driver voltages(Yoh, Vol), this standard will refer to output driver
44、impedances. Through reference to driverimpedance the driver characteristics will become easier to define and the resultant driverbehavior under various loading conditions will be easier to predict. For the expected values fordriver impedance and the parametrics associated with the drivers (see secti
45、on 4).2.2 InteroperabilityIt is expected that a group of devices of different supply voltages VDD will communicate with acommon communication voltage VDDQ which is equal to or less than VDD_low, the lowestsupply voltage of the group. Although it is desirable that chips of supply voltage VDD operateo
46、ver the largest possible range ofVDDQ, to meet this standard it is sufficient that chips ofVDDspecified in table 2-3 support communication at the associated values of VDDQ, with the Vii,Vih specifications oftable 2-2.Table 2-3 - Relationship between VDD, VDDQ, and VrefVDD VDDQ Vref1.5V l.5V, 1.2V, l
47、.OV 0.75V, 0.6V, 0.5V1.2V 1.2V, 1.0V, 0.8V 0.6 V, 0.5V, OAV1.0V l.OV,0.8V 0.5 V, OAVThe relationship is roughly VDDVDDQ0.6 x VDDJEDEC Standard No. 67Page 522Interoperability (contd)Similarly the I/O drivers associated with a semiconductor device operating with external voltageVOO must be capable of
48、providing an output voltage, satisfying the input requirements Vii andVih oftable 2-2 for a receiver configured for any associated VOOQ in table 2-3, at the specifiedimpedance. Separate VOOQ pins are recommended but not required. Separate VSS and VSSQpins are acceptable but not required.3 Flexible I
49、/O interface receiver3.1 Receiver typesA receiver covered in this section differentiates between a voltage sampled at the receiver inputbeing greater or less than some switch point or reference voltage Vref. To provide someimmunity to noise and various factors that effect receiver operation such as temperature, voltage,and circuit feature sizes and material properties, the switch point is in general associated with arange, described by its limits Vih_min at the high end and ViI_max at the low end. Section 1 and2 of this document defines these numbers for various supply voltages V
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