JEDEC JESD69B-2007 Information Requirements for the Qualification of Silicon Devices《硅仪器鉴定用信息要求》.pdf

1、JEDEC STANDARD Information Requirements for the Qualification of Silicon Devices JESD69B (Revision of JESD69A, October 2006) OCTOBER 2007 (Reaffirmed: JUNE 2011) JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and ap

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9、: JEDEC Solid State Technology Association 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 or refer to www.jedec.org under Standards-Documents/Copyright Information. JEDEC Standard No. 69B -i- INFORMATION REQUIREMENTS FOR THE QUALIFICATION OF SILICON DEVICES Introduction Customers ut

10、ilize supplier information when performing component qualification. This information typically includes quality, reliability, electrical and mechanical performance data. In addition, customers frequently request the supplier to complete a profile, or fact sheet, on the component or component family

11、being evaluated. This profile may include information on the materials used within the component as well as the location of the components manufacture or test. This profile, coupled with the above mentioned data elements, support the customers evaluation of a devices suitability for use in their app

12、lication. JEDEC Standard No. 69B -ii- JEDEC Standard No. 69B Page 1 INFORMATION REQUIREMENTS FOR THE QUALIFICATION OF SILICON DEVICES (From JEDEC Board Ballot JCB-99-10, JCB-06-57, and JCB-07-92, formulated under the cognizance of the JC-14.3 Committee on Silicon Devices Reliability Qualification an

13、d Monitoring.) 1 Scope This standard is intended to apply to silicon devices. This standard defines the requirements for the component qualification package which the supplier provides to the customer. It is intended to establish a minimum set of data elements, rather than to define the full range o

14、f possible customer information requests. Customers who require additional information will have to negotiate these requests with the supplier. This standard does not define which qualification method be followed (e.g., JESD47, JESD94, JP001, or JESD201), what tests must be performed, nor the qualif

15、ication performance levels (e.g. reliability or quality) that a component must satisfy. Rather, it establishes a set of data elements that describes the component. It requests the supplier to provide the test results of their qualification efforts. Customers are responsible for determining the exten

16、t to which supplier provided information will be used as part of their qualification process. 2 Reference documents JESD47, Stress Test Driven Qualification of Integrated Circuits JESD94, Application Specific Qualification Using Knowledge Based Test Methodology JP001, Foundry Process Qualification G

17、uidelines JEP95, JEDEC Registered and Standard Outlines for Solid State and Related Products J-STD-020, Moisture/Reflow Sensitive Classification for Nonhermetic Solid State Surface Mount Devices JESD22-A113, Preconditioning of Plastic Surface Mount Devices Prior to Reliability Testing JESD201, Envir

18、onmental Acceptance Requirements for Tin Whiskers Susceptibility of Tin and Tin Alloy Surface Finishes JEDEC Standard No. 69B Page 2 3 General requirements When requested, the supplier shall provide a qualification package to the customer. Based upon the customer/supplier agreed to completion date a

19、nd the actual completion of all testing and analysis, this qualification package shall be made available to the customer within two weeks of all work being completed. If a final report cannot be completed within 2 weeks a preliminary report should be made available in its place. The elements below s

20、hould be completed, where applicable, for all components that were utilized as part of the qualification, not only the device being qualified. This will enable generic or family data to be used in the qualification. The qualification package may be provided electronically or in a hard copy format an

21、d shall contain the following: A: Device Identification B: General Information C: Die Fabrication D: Package Assembly E: Electrical Test F: Supporting Data Listed below is the minimum set of data elements for each of the six items listed above: A: DEVICE IDENTIFICATION 1. Part Number and Revision: T

22、he suppliers part number and device revision level 2. Device Marking: The top side marking of the device. Include a description of any codes used. 3. Die Marking: The marking on the die which identifies the device. B: GENERAL INFORMATION (If the device has more than 1 die, state information for each

23、 die.) 1. Technology and Device Type: Technology identifier, minimum physical feature size and device family (e.g., 0.5um CMOS, 16M DRAM). 2. Package Type: The package style and other unique attributes (if applicable, JEP95). 3. Pin Count: Number of external connections. 4. Die Size: Die dimension:

24、length, width, and thickness (units). 5. MSL Moisture Sensitivity Level: Moisture Sensitivity Rating of component (e.g., J-STD-020) and peak reflow temperature the rating applies to. JEDEC Standard No. 69B Page 3 3 General requirements (contd) C: DIE FABRICATION (If the device has more than 1 die, s

25、tate information for each die.) 1. Fabrication Process Identifier, if applicable: A unique code or description which identifies the specific fabrication process. 2. Fabrication Supplier Name: If subcontracted, name of the subcontracted company that owns the fabrication site. If there are multiple fa

26、b suppliers, state all covered by this report. 3. Fabrication Location(s): The country, state (if applicable), and city where the device is fabricated. If there are multiple fabs or fab lines at this location, state fab number/name and/or Line number/name. 4. Die Metallization and Number of Levels:

27、Composition of the die metallization and number of separate levels of metallization. 5. Die Protective Coating: Composition and thickness of topmost level of protection and coating on the die which may include more than one layer (e.g. passivation layers, polyimide wafer coats, liquid dispensed die

28、coats). 6. Bond Pad or UBM (Under Bump Metallurgy) Composition, Thickness and Pitch: Composition, thickness, and pitch of wirebond pad or UBM. 7. Die Substrate Material: Starting material (e.g., SOI, Si, epi). D: PACKAGE ASSEMBLY 1. Assembly Process Identifier, if applicable: A unique code or descri

29、ption which identifies the specific assembly process, if applicable. 2. Assembly Supplier Name: If subcontracted, name of the subcontracted company that owns the assembly site. If there are multiple assembly suppliers, state all covered by this report. 3. Assembly Location(s): The country, state (if

30、 applicable), and city where the device is assembled. 4. Leadframe or Substrate Type: Base material, number of core and build up layers (substrates only), finish and critical dimensions. 5. Die-to-Die and/or Die-to-Package Interconnect: Type (e.g., TAB, wire bond, flipchip), metal composition, dimen

31、sions. 6. Die Attach, if applicable: Material, process and/or die attach technique to attach die to leadframe/substrate or to another die. 7. Package Material and Flammability Rating if plastic: Package material or composition (e.g., mold compound, underfill, hermetic package) and flammability ratin

32、g, if plastic. 8. Terminal Finish or Solder Ball Material: Composition and proportion of the material(s) used as terminal frame finish (including tin whisker mitigation techniques used on tin and tin alloy finishes) or solder ball (for BGAs). JEDEC Standard No. 69B Page 4 3 General requirements (con

33、td) E: ELECTRICAL TEST 1. Electrical Test Supplier Name: If subcontracted, name of the subcontracted company that owns the electrical test site that performs final functional test. If there are multiple test suppliers, state all covered by this report. 2. Electrical Test Location: The country, state

34、 (if applicable), and city of final electrical test. F: SUPPORTING DATA Results of the Suppliers Internal Qualification: All tests performed to evaluate the quality, reliability and mechanical performance of the device. This can include internal evaluations, user-specific requirements, in-process mo

35、nitors, and process/product change requalifications. 1. Test Performed: Test performed and stress conditions associated with this test (e.g., temperature, voltage, humidity). 2. Test Vehicle(s): Device(s) used to generate qualification data (e.g., part number and revision level). 3. Preconditioning:

36、 Conditions used in the simulation of the component attach process prior to stress testing (e.g., JESD22-A113). 4. Burn-in Conditions (if performed): If the product tested was burned-in prior to reliability stress testing, state the burn-in conditions (e.g., temperature, voltage, duration). 5. Sampl

37、e Sizes: Number of samples used in the test and maximum number of failures allowed for acceptance. 6. Fail Criteria: The method used to assess whether a device has passed or failed a given test (e.g., electrical testing, mechanical integrity). 7. Test Results: The number of devices which pass or fai

38、l the test criteria. 8. Duration: The number of hours, cycles, etc. which devices were subjected to during the test. 9. Failure Analysis Results: The summarized results of any physical analysis of failures including an identification of the root cause, failure mechanism, and corrective action. 10. C

39、onstruction Analysis Results: Results of a construction analysis if one was performed (e.g., cross-section, C-SAM, x-ray, visual inspection, ball shear) JEDEC Standard No. 69B Page 5 3 General requirements (contd) If generic or family data was used (e.g., family qualification, library qualification,

40、 or qualification by similarity), the following information for the Test Vehicle(s) must be provided if it is different from the device being qualified. a. Part Number and Revision b. Technology and Device Type c. Package Type d. Pin Count e. Fabrication Supplier Name f. Fabrication Location g. Asse

41、mbly Supplier Name h. Assembly Location i. Die Protective Coating j. Leadframe or Substrate Type k. Die Attach l. Package Material m. Terminal finish (including any tin whisker mitigation technique) or solder ball material JEDEC Standard No. 69B Page 6 Annex A (informative) Differences between JESD6

42、9B and JESD69A This table briefly describes most of the changes made to entries that appear in this standard, JESD69B, compared to its predecessor, JESD69A (October 2006). If the change to a concept involves any words added or deleted (excluding deletion of accidentally repeated words), it is includ

43、ed. Some punctuation changes are not included. Page Description of change 1 In Clause 1, 2ndparagraph; added JESD201 1 In Clause 2, added reference JESD201 3 In clause 3D, item 8; changed “Lead” to “Terminal” 3 In clause 3D, item 8; added “(including tin whisker mitigation techniques used on tin and

44、 tin alloy finishes)” 5 In clause 3; added item m Standard Improvement Form JEDEC JESD69B The purpose of this form is to provide the Technical Committees of JEDEC with input from the industry regarding usage of the subject standard. Individuals or companies are invited to submit comments to JEDEC. A

45、ll comments will be collected and dispersed to the appropriate committee(s). If you can provide input, please complete this form and return to: JEDEC Attn: Publications Department 2500 Wilson Blvd. Suite 220 Arlington, VA 22201-3834 Fax: 703.907.7583 1. I recommend changes to the following: Requirement, clause number Test method number Clause number The referenced clause number has proven to be: Unclear Too Rigid In Error Other 2. Recommendations for correction: 3. Other suggestions for document improvement: Submitted by Name: Phone: Company: E-mail: Address: City/State/Zip: Date: