JEDEC JESD7-A-1986 54 74HCXXXX and 54 74HCTXXXX High Speed CMOS Devices Description of (Erratum - August 1986)《54 74HCXXXX和54 74HCTXXXX高速CMOS器件 勘误 描述1986年8月》.pdf

1、- EIA JESD7-A 6 m 3234600 0005743 5 m f +filE PR0 JEDEC Solid State Products 2001 Eye Street, Engineering NW Council “).cERl“G CQ Washington D.C. 20006 (202) 457-6971 August 29, 1986 ERRATUM TO JEDEC STANDARD NO. 7-A The Engineering Department of the Electronic Industries Association recently publis

2、hed the above referenced Standard titled “Standard for Description of 54/74HCXXXX and High Speed CMOS Devices“. Unfortunately, we have discovered some errors in the document. are editorial in nature rather than technical and will note change the content of the Stan- dard. Pages 2 and 5, paragraph 3.

3、2: 54/74HCTXXXX We believe these errors Please correct your copy as follows: Change tr, tf to “tr, tf“ Page 8: Supplement the Figure below with the one contained in the document. Page 18, HC/HCT4538 under TEST CONDITIONS: Change Io to 10. Page 19, under 6.2 Change twQ to IrtWQrl in three places. Not

4、e that the above corrections will be incorporated at the next reprint of JEDEC Standard NO. 7-A. TWX (710) 822-0148 Telefax (202)457-4985 lf-L-7 EIA JESD7-A b m 3234b00 0005744 7 m -. AUGUST 1986 JEDEC STANDARD NO. 7-A STANDARD FOR DESCRIPTION OF 54174HCXXXX AND 54/74HCTXXXX HIGH SPEED CMOS DEVICES

5、JEDEC Solid State Products Engineering Council EIA JESD7-A 86 323LIbOO 0005745 9 W 1 NOTICE This JEDEC Standard or Publication contains material that has been prepared, progressively reviewed, and approved through the JEDEC Council level and subsequently reviewed and approved by the EIA General Coun

6、sel. JEDEC Standards and Publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the prope

7、r product for his. particular need. Existence of such standards shall not in any respect preclude any member or nonmember of JEDEC from manufacturing or selling products not conforming to such standards, nor shall the existence of such standards preclude their voluntary use by those other than EIA m

8、embers whether the standard is to be used either domestically or internationally. Recommended Standards are adopted by JEDEC without regard to whether or not their adoption may involve patents or articles, materials, or processes. By such action JEDEC does not assume any liability to any patent owne

9、r, nor does it assume any obligation whatever to parties adopting the JEDEC Standards or Publicat ions. The information included in JEDEC Standards and Publications represents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. W

10、ithin the JEDEC organization there are procedures whereby a JEDEC Standard or Publication may be further processed and ultimately become an EIA Standard. Inquiries, comments, and suggestions relative to the content of this JEDEC Standard or Publication should be addressed to the JEDEC Executive Secr

11、etary at EIA Headquarters, 2001 Eye Street, N.W., Washington, D.C. 20006. Published by ELECTRONIC INDUSTRIES ASSOCIATION Engineering Department 2001 Eye Street, N.W. Washington, D.C. 20006 Copyright 1986 ELECTRONIC INDUSTRIES ASSOCIATION All rights reserved PRICE: $27.00 Printed in U.S.A. L -? EIA J

12、ESD7-A 8b m 3234600 000574b O m JEDEC Standard No. 7A STANDARD FOR DESCRIPTION OF. 54/74HCXXXX AND 54/74HCTXXXX HIGH SPEED CMOS DEVICES (From JEDEC Council Letter Ballot JCB-86-5, formulated under the cognizance of EIA/JEDEC JC40.2 Committee on CMOS Logic Devices. ) 54/74HCXXXX - TABLE 1 - 54/74HCTX

13、XXX - TABLE 2 - APPENDIX A - APPENDIX B - APPENDIX C - APPENDIX D - APPENDIX E - APPENDIX F - TABLE OF CONTENTS STANDARD BC SPECIFICATION 54/74HCXXXX STANDARD DC SPECIFICATION 54/74HCTXXXX SWITCHING WAVEFORMS Icc AND OUTPUT DRIVE CATEGORIES PER DEVICE TYPE NON-STANDARD DEVICE SPECIFICATIONS SWITCHIN

14、G SPEED STANDARDS CPD DEFINITION AND TABLE OF TEST CONDITIONS REFERENCE TO APPLICABLE JEDEC STANDARDS -CHIP CARRIER MAPPING FROM DIP -LOW VOLTAGE -PACKAGE OUTLINES PAGE 1 3 4 6 7 12 13 33 80 93 -I- -. 1. EIA JESD7-A b m 3234b00 0005747 2 m JEDEC Standard No. 7A Page 1 54/74HCXXXX STANDARD PURPOSE AN

15、D SCOPE 1.1 Purpose: To develop a standard of It54/74HCXXXXlt series specification to provide for uniformity, multiplicity of sources, elimination of confusion, and ease of device specification and design by users. 1.2 Scope: This Standard covers standard specifications for description of lt54/74HCX

16、XXXI1 Series High-speed Silicon Gate CMOS devices. 2. DEFINITIONS 2.1 t154/74HCXXXX1t series includes buffered devices whose input logic levels are defined herein for VIH and VIL. 2.2 A buffered device has two or more active logic stages between inputs and outputs. 2.3 ii54tt indicates that the devi

17、ces are specified over the 2.4 ii74t1 indicates that the devices are specified over the temperature range -55 to 125C. temperature range -40 to 85C. 3. STANDARD SPECIFICATIONS All voltages listed are referenced to ground except where noted EIA JESD7-A b W 3234b00 0005748 4 W JEDEC Standard No. 7A Pa

18、ge 2 3.1 ABSOLUTE MAXIMUM RATINGS(N0TE 1) : Supply Voltage vcc DC Input Diode Current - IIK OR - DC Input Voltage. VI DC Output Diode Current IOK OR DC Output Voltage VO DC Output Source or IO Sink Current, Per Output Pin DC VCC or Ground Current Icc or IGND Storage Temperature Tstg 3.2 Recommended

19、Operation Conditions: Supply Voltage (NOTE 2) vcc Input Voltage VI Output Voltage VO Operating Temperature TA 74HC 54HC Input Rise and Fall Time tr, tf at 2.0V (Except for Schmitt Inputs) at 4.5V at 6.0V -0.5 to 7.0 VI o VI vcc -0.5 to vcc +0.5 VO c o vo vcc -0.5 to vcc +0.5 f25 (STD) f35 (Bus Drive

20、r) f70 (Bus Driver) 150 (STD) -65 to 150 2.0 to 6.0 o to vcc o to vcc -40 to 85 -55 to 125 o to 1000 O to 500 O to 400 I V -20 mA 20 mA V -20 mA 20 mA V mA mA nlA mA “C O V V V “C “C ns ns ns NOTE 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional op

21、eration under these conditions is not implied. NOTE 2: Unless otherwise specified. EIA JESD7-A b m 3234b00 0005749 b m J. 4 I I 3.3 DC SPECIFICATIONS I 1 I I I I vcc I IV SIMBI PARAMETER 1 VIH I HIGH LEVELI2.O I INPUT 14.5 I VOLTAGE 16.0 I I VIL I LOW LEVEL 12.0 I INPUT 14.5 I VOLTAGE 16.0 I I I I I

22、 I I I I VOH I HIGH LEVELI2.O I OUTPUT 14.5 NOTEI VOLTAGE 16.0 14.5 16.0 11 I i I VOL I LOW LEVEL 12.0 I OUTPUT (4.5 JEDEC Standard 7A Page 3 (TABLE 1) 54/74HC FAMILY SPECIFICATIONS Temperature C 54HC/74HC I 74HC I 54HC 25 1 -40 TO 851 -55 TO 125 MIN IMAX I MIN IMAX I MIN I MAX 1.501 I 1.501 I 1.501

23、 3.15i 1 3.151 i 3.35i 4.201 I 4.201 I 4.201 I I I 10.301 10.301 10.30 10.901 10.901 1090 11.201 Ii.20l 11.20 I I I I I I I I I I 1 I 1k0.51 1k5.01 IIl0.C I I I I I I I I I I CABLE TO OPEN DmIN OUTPUTS i2 j FOR DIGITAL 110 PINS USE LIMITS (3) (4) SEE APPENDIX B ALSO APPLICABLE FOR OPEN DRAIN OUTPUTS

24、 JI XI r I CONDITIONS VI VI VI i I TEST VI vi I l I NOTE 4 i 1 STD JBUS V IVIHI -20.01-20.0 V I OR1 -20.01-20.0 V I I - 4.01- 6.0 V VILI - 5.21- 7.8 V IVIHI 20.01 20.0 V I OR1 20.01 20.0 V I I 4.01 6.0 V lV1-1 5.21 7.8 I IO v I I -20.0-20.0 L v I I 20.01 20,o - u N I T UA UA UA na mA UA UA UA mA mA

25、- - /- JEDEC Standard Page 4 EIA JESD7-A b W 3234b00 0005750 2 W 1 No. 7A 54/74HCTXXXX STANDARD 1. PURPOSE AND SCOPE 1.1 Purpose: To develop a standard of “54/74HCTXXXIt series specifications to provide for uniformity, multiplicity of sources, elimination of confusion, and ease of device specificati

26、on and design by users. 1.2 Scope: This Standard covers standard specifications for description of 1154/74HCTXXXX1t series High-speed Silicon Gate CMOS devices which are functionally and parametrically similar to 1154/74LSXXX11 devices. 2. DEFINITIONS 2.1 t154/74HCTXXXXtt series includes devices who

27、se input logic 2.2 i15411 indicates that the devices are specified over the levels are TTL input levels. temperature range -55 to 125C. 2.3 tt74t1 indicates that the devices are specified over the temperature range -40 to 85C. 3. STANDARD SPECIFICATIONS All voltages listed are referenced to ground e

28、xcept where noted. 4. .- EIA JESD7-A 86 m 3234b00 0005753 4 m 3EDEC Standard No. 7A Page 5 0 3.1 ABSOLUTE MAXIMUM RATINGS(N0TE 1) : Supply Voltage vcc DC Input Diode Current IIK OR _. DC Input Voltage VI DC Output Diode Current IOK OR - DC Output Voltage VO DC Output Source or IO Sink Current, Per O

29、utput Pin DC VCC or Ground Current Icc or IGND Storage Temperature Tstg 3.2 Recommended Operation Conditions: O Supply Vqltage (NOTE 2) Input Voltage Output Voltage Operating Temperature -0.5 to 7.0 VI , a !, VOL/VO, outputs specifications EIA JESD7-A b W 3234600 0005759 9 W J. JEDEC Standard No. 7A

30、 Page 13 flJxmwxc DEVICE SPECIFICATIONS This appendix describes individual device specifications that are either not covered by the main standard or are special exceptions to this standard due to device functional, design, or application considerations. Paragraph 1 .o 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0

31、 10.0 11.0 12.0 Device Description HWHC.4543 Output Drive and Transition Time HC/HCT4511 Output Drive Specifications HC4049/50 Input and IW Specifications Parts with On-Chip Oscillators Schmitt-trigger Input Specifications Monostable Multivibrator Ia and Pulse Width Quad Analog Switch Specifications

32、 Specifications for Analog Multiplexers, and Phase Lock Loop Specifications Hm04 DC Specification Definition of -1, -2 Part Number Suffixes HC682 Input Leakage and ICc Specifications Specifications Specifications. Switches with Level Translators I- - EIA JESD7-A 8b W 3234b00 00057b0 5 t r erature oc

33、 S REm=10 kQ , CEm=O.l PF Output Pulse 5.0 0.90 1.10 0.86 1.14 0.85 1.15 ms Width IIIIIIIII HC/HCT123, HC/HCT423; R-=10 kQ , CEm=O.l PF Recomnended range of component values for ItEXT, CEm applicable over appropriate temperature range. EIA JESD7-A 8b 3234600 00057bb b 7 7.3 Additional DC Electrical

34、Characteristics . erature oc U N SYMB PARAMETER I V MINMAXMINMAXMINMAX T High Level 9.0 6.30 6.30 6.30 V IH input Voltage VIL Low Level 9.0 ; 1.80 1.80 1.80 V RON ON Resistance 4.5 180 225 270 Q RON Peak ON Resis- 4.5 320 400 480 52 tance (4016) 9.0 170 215 255 Q RON ON Resistance 4.5 85 106 130 Q I

35、nput Voltage (4016) 9.0 135 170 205 Q - - (4066) 9.0 63 78 95 52 RON Peak ON Resis- 4.5 170 215 255 Q c tance (4066) 9.0 85 106 130 Q ICc Quiescent HCT 5.5 2.0 20 40 pA Current HC 10.0 16.0 160 320 pA IIz Switch HCT 5.5 LO.1 5.0 10 pi ON/OFF HC 6.0 kO.1 5.0 &lo Leakage HC 10.0 LO.1 5.0 10 pA Supply

36、HC 6.0 2.0 20 40 FA I JEDEC Standard No. 7A Page 20 I TEST COM)ITIONS I VISGND or V Is- c2.0 A*vI%IH S- VIs=GND or V Is- c2.0 A*vI%IH V Is- VI=GND or Vcc VIs=GND or V vos=v or GE VI =VIL or VIH 7.0 E/EKX 4016. Hc/HCi4 066. Oua d Analop Switches. These parts have the following extended specifications

37、. Standard VoH and VOL specifications under loaded conditions may not apply. supply Voltage (V,) BC -0.5 V to 11.0 V 7.1 Ext ended Absolut e Maximum Ratiw HCT -0.5 V to 7.0 V *. 7.2 &tended Recanmended ODeratinp Conditions supply Voltage -0.5 v to +7.0 v Supply Voltage (VEE) +0.5 v to -7.0 v supply

38、Voltage (VW-VEE) -0.5 V to +.O V 8.2 Btended Reemanended Qgeratim&nditions Supply Voltage (VE HC 2.0 V to 6.0 V HCT 4.5 v to 5.5 v 0.0 V to -6.0 V Supply Voltage (vEE) Supply Voltage (V -V ) 2.0 v to 10.0 v Dc Input Voltage (VI) 0.0 v to vm DC input Voltage (V (see Figure F2.T5 (digital inputs) (ana

39、log inputs VEE to Vcc Refer to individual manufacturers data sheets for limitations on DC voltage drop across each switch and current through the switch. 1 + ! 1 a 1 2 3 4 5 6 7 8 9 10 (VK-VEE) Figure 8.2.1 Recomnended Power Supply Range EIA JESD7-A Bb 3234b00 0005771 T 9 JEDEC Standard No. 7A Page

40、25 8.3 Additional DC Electri cal Characteristlcs 8.3.1 Qn-Res is tance Charac ter is tics vcc PARAMETER ON Resistance (51,52,53) Peak ON Resis- tance (51,52,53) ON Resistance ( 4366) Peak ON Resis- tance (4316) : 4.5 v- I TEST c0M)ITIONS I O 8.3.2 Leakage Characteristic-8 PARAMETER - EIA JESD7-A 86

41、m 3234600 0005772 I m JEDEC Standard No. 7A Page 26 8.3.3 SUDIV C urrent Char acteristics e PARAMETER 0.0 6.0 TEST CONDI TI ONS VI=GND or VE 1 vcc PARAMETER r I Minimum Frequency 2.15 Response (-3dB) 4.50 Crosstalk Between 2.25 any Two Switches 4.50 Control to Switch 2.25 Feedthrough Noise -4.50 I (Beak to Peak) Switch OFF Signal 2.25 Feedthrough 4.50 I s o1 at i on Total Harmonic 2.25 Distortion 4.50 4 -2.29 -4.58 -2.25 -4.50 -2.25 -4.50 -2.25 1-4.50 i-2.25 1-4.50 U N TEST I CONDITIONS T Figure 8.4.1 I I Figure 8.4.2 Figure 8.4.3 I- l