JEDEC JESD70-1999 2 5 V BiCMOS Logic Device Family Specification with 5 V Tolerant Inputs and Outputs《具有5伏容忍输入输出的2 5 V BiCMOS逻辑设备系列规范》.pdf

1、STD=EIA JESD7O-ENGL 1999 II 323rib00 Ob2284L 3T7 E EIA/JEDEC STANDARD 2.5 V BiCMOS Logic Device Family Specification with 5 V Tolerant Inputs and Outputs JESD7O JUNE 1999 ELECTRONIC INDUSTRIES ALLIANCE JEDEC Solid State Technology Association - - Eiectronk Inastrlcs Alllana STD-EIA JESD70-ENGL 1999

2、3234600 Ob22842 235 NOTICE EWJEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors level and subsequently reviewed and approved by the EIA General Counsel. EWJEDEC standards and publications are designed to serve the pub

3、lic interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the st

4、andard is to be used either domestically or internationally. EWJEDEC standards and publications are adopted without regard to whether or not their adoption may involve patents or articles, materials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it as

5、sume any obligation whatever to parties adopting the EWJEDEC standards or publications. The information included in EWJEDEC standards and publications represents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDE

6、C organization there are procedures whereby an EWJEDEC standard or publication may be further processed and ultimately become an ANSEIA standard. No claims to be in conformance with this standard may be made unless all requirements stated in the standard are met. Inquiries, comments, and suggestions

7、 relative to the content of this EWJEDEC standard or publication should be addressed to JEDEC Solid State Technology Association, 2500 Wilson Boulevard, Arlington, VA 22201-3834, (703)907-7560/7559 or www.jedec.org Published by ELECTRONIC INDUSTRIES ALLLANCE 1999 Engineering Department 2500 Wilson B

8、oulevard Arlington, VA 2220 1-3834 “Copyright“ does not apply to JEDEC member companies as they are free to duplicate this document in accordance with the latest revision of JEDEC Publication 2 1 “Manual of Organization and Procedure“. PRICE: Please refer to the current Catalog of JEDEC Engineering

9、Standards and Publications or call Global Engineering Documents, USA and Canada (1-8OO-854-7179), International (303-397-7956) Printed in the U.S.A. All rights reserved STD-EIA JESD70-ENGL 1999 3234600 Ob22843 L7L = JEDEC Standard No. 70 Page 1 2.5 V BiCMOS LOGIC DEVICE FAMILY SPECIFICATION WITH 5 V

10、 TOLERANT INPUTS AND OUTPUTS (From JEDEC Board Ballot JCB-98-43, formulated under the cognizance of the JC-40 Committee on Digital Logic.) 1 Purpose The purpose is to provide a standard for 2.5 V nominal supply voltage logic devices, for uniformity, multiplicity of sources, elimination of confusion,

11、 ease of device specification, and ease of use, thus providing compatibility between devices operating between 2.3 V and 2.7 V supply voltages, as well as overvoltage tolerance with devices operating at 3.3 V, or 5 volts. 2 Scope This standard defines dc interface parameters and test loading for dig

12、ital logic devices based on 2.5 V (nominal) power supply levels. 3 Terms and definitions prefixes: Prefixes “54“ or “74“ immediately preceding family name indicate the operating temperature range. For example, 54xxx refers to Miiitary (MIL) version of devices that are specified over the temperature

13、range of -55 “C to +125 OC. 74xxx refers to the Commercial (COML) version of devices that are specified over -40 OC to +85 OC. STDmEIA JESD70-ENGL 1999 I 3234600 Ob22844 008 I referenced to GND (ground = OV) PARAMETER I CONDITIONS I RATING I UNIT JEDEC Standard No. 70 Page 2 DC supply voltage DC inp

14、ut voltage DC output voltage 4 Standard specifications -0.5 to +3.6 V -0.5 to +7.0 V Output in OFF state -0.5 to +7.0 V 4.1 Absolute maximum continuous ratings“ Storage temperature range VOUT -65 to +150 “C High-level input voltage input voltage High-level output current Low-level output current Inp

15、ut transition rise or fall rate; Outputs enabled Operating free-air temperature range 1.7 V 0.7 V -8 mA 24 mA 10 nsN -40 +85 “C NOTES 1 Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated

16、may adversely affect device reliability. Functional operation under these conditions is not implied. 2 Under transient conditions these ratings may be exceeded as defined elsewhere in this specification. 4.2 Recommended operating conditions I VDD I VI p AtJAv PARAMETER DC supply voltage I 2.3 I 2.7

17、I V I input voltage Io 15.5 Ivl STD=EIA JESD70-ENGL 1999 3234h00 Oh22845 T44 VDD = 2.3 V; IIK = -18 mA VDD = 2.3 V; IOH = -8 mA VDD = 2.3 to 2.7 V; IOH = - 100 pA JEDEC Standard No. 70 Page 3 -1.2 . v VDD - 0.2 1.8 V 4 Standard specifications (contd) 4.3 DCspecifications Over recommended operating c

18、onditions. Voltages are referenced to GND (ground = O V) VOL II SYMBOL PARAMETER Low-level output voltage Input leakage current vIK I Input clamp voltage High-level output voltage VoH I 10m I Output off current current2 output current3 Ipup Power up/down State NOTES TEST CONDITIONS Temp = -40 OC to

19、45 OC UNIT c VIH I VIH I VDD = 2.7 V; Vo = 0.5 V; VI = VIL or I I -5 I PA VIH 1 Untested pins at VDD or GND. YO pins to be configured as inputs. 2 This parameter not applicable for YO pins. See II/O for leakage currents on I/O pins. 3 This parameter is valid for any VDD between O V and 1 .O V with a

20、 transition time of up to 10 ms. From VDD = 1 .O V to VDD = 2.5 V f 0.2 V a transition time of 100 ps is permitted. STDmEIA JESD70-ENGL 1999 I 3234b00 Ob22846 980 I JEDEC Standard No. 70 Page 4 4 Standard specifications (contd) 4.4 Power supply characenstics LIMITS SYMBOL kCH kcz2 PARAMETER hiescent

21、 supply :urrent TEST CONDITIONS VDD = 2.7 V; Outputs High, VI = GND Or VDD. r0 = 0 VDD = 2.7 V; Outputs Low, VI = GND VDD = 2.7 V; Outputs Disabled; VI = Or VDD, r0 = 0 GNDOrvDD Temp = -40 OC to +85 OC MIN - MAX 100 300 100 UNIT NOTES: 1 The total current for this parameter is the current per output

22、 times the number of outputs in this state. 2 kcz is measured with outputs pulled up to VDD or pulled down to ground. STD.EIA JESD70-ENGL L999 I 3234b00 Ob22847 BL7 II tpLH (except open-collector outputs) Open tpm (open-collector outputs) tpHL (except open-collector outputs) Open tpHL (open-collecto

23、r outputs) tPZH GND tPZL voo x 2 tPhZ GND VD0 x 2 voo x 2 tPK vmx2 JEDEC Standard No. 70 Page 5 5 Test circuit and waveforms DEFINiTlONS RL = RI = 500Q or equivalent. CL = 30 pF or equivalent (includes jig and probe capacitance). RT = of pulse generator (typically 50R ). OUTPUTS ARE MEASURED ONE AT

24、A TIME WITH ONE TRANSTION PER MEASUREMEM. I CVoozpi Figure 1 - Test circuit STD*EIA JESD70-ENGL 1999 I 3234b00 Ob22846 753 JEDEC Standard No. 70 Page 6 5 Test circuit and waveforms (contd) 5.1 Switching waveforms VM = vDD/2, vm = GND to VDD Vx = VOL + 150 mV Vy = VOH - 150 mV SyooM6 Figure 3 - Pulse

25、 Duration (Width) Measurements V“ Figure 4 - Setup and Hold Time Measurements I STDeEIA JESD70-ENGL 1999 I 3234600 0622849 b9T I JEDEC Standard No. 70 Page 7 5 Test circuit and waveforms (contd) 5.1 Switching waveforms (contd) VOH v,on * _- -0v -_-_-_- OUTPUT Hgh.2 IO Hgh SVM)2w Figure 5 - Enable Time Measurements I VOL -4- - - - - - I I Figure 6 - Disable Time Measurements 6 Reference to other applicable JEDEC standards and publications JEDEC Standard No. 8-5 2.5 V for Non-terminated Integrated Circuit. (EWJEDEC 8-5) 0.2 V (Normal Range), Power Supply Voltage and Interface Standard