JEDEC JESD73-3-2001 Standard for Description of 3867 2 5 V 10-Bit 2-Port DDR FET Switch《3867 2 5 V 10位 2端口 DDR FET交换的描述标准》.pdf

1、JEDEC STANDARD Standard for Description of 3867: 2.5 V, Single 10-Bit, 2-Port, DDR FET Switch JESD73-3 NOVEMBER 2001 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors l

2、evel and subsequently reviewed and approved by the EIA General Counsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandmgs between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the

3、 purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. JEDEC standards and publications are adopted without regard to whether or not their adoption may involve p

4、atents or articles, materials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or publications. The information included in JEDEC standards and publications represents a sound app

5、roach to product specification and application, principally fiom the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby an JEDEC standard or publication may be further processed and ultimately become an ANSEIA standard. No claims to be in conformanc

6、e with this standard may be made unless all requirements stated in the standard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC Solid State Technology Association, 2500 Wilson Boulevard, Arlington, VA 22201-3834

7、, (703)907-7559 or www.jedec.org Fublished by OJEDEC Solid State Technology Association 200 1 2500 Wilson Boulevard Arlingtq VA 22201-3834 This document may be downloaded free of charge; however JEDEC retains the copyright on this material. By downloading this file the individual agrees not to charg

8、e for or resell the resulting material. PRICE: Please refer to the current Catalog of JEDEC Engineering Standards and Publications or call Global Engineering Documents, USA and Canada 1-800-854-7179, International (303) 397-7956 Printed in the U.S.A. All rights reserved JEDEC Standard No. 73-3 Page

9、1 Standard for Description of 3867: 2.5 V, Single IO-bit, 2-port, DDR FET Switch (From Board Ballot JCB-01-65, formulated under the cognizance of the JC-40.2 Subcommittee on Bus Switch Logic Products.) 1 Scope This standard covers the specification for the 3867, 2.5 V, FET transmission-gate bus swit

10、ch device with 2.5 V LVTTL compatible control inputs. Not included in this document are device specific parameters and performance levels that the vendor must also supply for the full device description. The purpose of this standard is to provide a set of uniform data sheet parameters for the descri

11、ption of the 3867, 2.5 V, DDR FET switch device. This standard includes required parameters, test conditions, test levels, and measurement methods for data sheet descriptions of the 3867,2.5 V, DDR FET switch device. NOTE The designation 3867 refers to the numerical portion of the part designation o

12、f a series of commercial logic parts common in the industry. This number is normally preceded by a series of manufacturer specific characters to make up a complete part designation. 2 Definitions for the purpose of this document switch device: A semiconductor logic device designed to connect or disc

13、onnect busses or control signals without active drivers in the connection path. connect: A state in a switch device is characterized by a minimum series impedance through the designated electrical path. disconnect: A state in a switch device is characterized by the high series impedance of the desig

14、nated electrical path. JEDEC Standard No. 73-3 Page 2 3 Standard specification 3.1 Device description This 1 O-bit, two-port bus switch is designed for 2.3 V to 2.7 V, VDD operation. All inputs are compatible with the JEDEC standard for 2.5 V, CMOS. The 3867 device is organized into one bank of IO-b

15、it, transmission-gate bus switches. The bank is enabled through an associated Bus Enable (BE), which is driven low to enable the switches and connect the A-port to the B-port. Driving BE high will disable the switches and disconnect the A-port from the B-port with a high impedance state. The 3867, i

16、s intended to be used with X8 SDRAM memory. The ninth and tenth transmission gate switches provide paths for overhead data. The BE pin does not have an internal pull-up resistor. The output pins on the B-side of the device are internally pulled down to ground reference through a weak resistor struct

17、ure to provide termination to the transmission gate switch channels. Package options for this device include thin small-outline package (MO-I 53 AD). 3.2 Logic block diagram and device pin configuration Figure 1 - Logic block diagram Figure 2 - Device pin configuration JEDEC Standard No. 73-3 Page 3

18、 Pin Name BE - 3 Standard specification (contd) Description Bus Enable Input (Active LOW) 3.3 Product pin description and truth table Function Disconnect Connect - BE AO-A9 BO-B9 H Hi-Z L L BO-B9 AO-A9 AO-9 I A-port Supply voltage range, VDD DC input voltage B 0-9 I B-port -0.5 V to +3.6 V -0.5 V to

19、 +3.6 V GND I Ground I Bus I/O Voltage to Ground Potential I -0.5 V to +3.6 V I I DC channel current I +I28 mA I Storage temperature 1-65 “C to 150 “C I NOTE Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional

20、 operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. JEDEC Standard No. 73-3 Page 4 Parameter VDD TA 3 Standard spe

21、cification (contd) 3.5 Recommended operating conditions Description Min. Max. Units Supply Voltage 2.3 2.7 V Operating Free-Air Temperature O +70 “C NOTE Unused device control inputs must be held at VDD or GND to ensure proper device operation. 3.6 DC electrical specifications Table 5 - Electrical c

22、haracteristics over recommended operating free-air temDerature ranae Parameter VIH VIL VIK IOZH RON Description H ig h-Level Input Voltage Low- Leve I Input Voltage Clamp Diode Voltage High i m pedance Output Current Switch ON Res istan ce* Test Conditions* Guaranteed Logic Level High Guaranteed Log

23、ic Level Low VDD = Min., IIN = -18 mA - BE= H B-Port I/O level = 2.5 V VDD = Min., VIN = 0.9 V, ION = 20 mA Min. I Typ: I I l7 22 Max. I Units -1.2 I v I 250 PA 33 I i2 I 30 I i2 * For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device

24、 type. t Typical values are at VDD = 2.5 V, TA = 25 “C ambient and maximum loading. $ Measured by the voltage drop between A and B pin at indicated current through the switch. ON resistance is determined by the lower of the voltages on the two (A, B) pins. JEDEC Standard No. 73-3 Page 5 Parameter* C

25、IN COFF CON (A/B) Description Max. Units Test Conditions Input Capacitance VIN = 0 v 3. O PF A Capacitance, Switch OFF VIN = 0 v 3. O PF A/B Capacitance, Switch ON VIN = 0 v 7.0 PF I * The parameters are determined by device characterization; not production tested. Parameter IDD Table 7 - Power suml

26、v characteristics i. Min. Typ.+ Max. Units Test Conditions* * Description 10 PA Quiescent power VDD = max - - supply current Parameters tPZH tPZL tPHZ tPLZ * For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device. t Typical values are

27、at VDD = 2.5 V, +25 “C ambient. $ Pins of A-port and B-port do not contribute to IDD. Comm. Min. Max. Description Test Conditions Units Bus Enable Time 1 3 BE to Ax or Bx CL= 30 pF, 1 3.5 Bus Disable Time RL = 500 i2 1 3 ns BE to Ax or Bx 1 3.8 3.7 AC specifications Table 8 - Switching characteristi

28、cs over recommended operating free-air JEDEC Standard No. 73-3 Page 6 4 Parameter measurements TEST I SI Open tP LZltPZL XVDD tP D tPHZ/tPZH GND VOLTAGE WAVEFORMS: PROPAGATION DELAY TIMES VOLTAGE WAVEFORMS: ENABLE AND DISABLE TIMES Figure 3 - Parameter measurements NOTE 1 CL includes probe and jig c

29、apacitance. NOTE 2 Waveform 1 is for an output with internal conditions such that the output is LOW except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is HIGH except when disabled by the output control. NOTE 3 All input pulses are supplied by generators having the following characteristics: PRR10 MHz, Z, = 50 Ci, tR = 2 ns, tF = 2 ns. NOTE 4 The outputs are measured one at a time with one transition per measurement.