1、JEDEC STANDARD Early Life Failure Rate Calculation Procedure for Semiconductor Components JESD74A (Revision of JESD74, April 2000) FEBRUARY 2007 (Reaffirmed: JANUARY 2014) JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, review
2、ed, and approved through the JEDEC Board of Directors level and subsequently reviewed and approved by the JEDEC legal counsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchan
3、geability and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. JEDEC standards and publications are adopted witho
4、ut regard to whether or not their adoption may involve patents or articles, materials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or publications. The information included in
5、 JEDEC standards and publications represents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may be further processed and ultimately b
6、ecome an ANSI standard. No claims to be in conformance with this standard may be made unless all requirements stated in the standard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC at the address below, or refer
7、 to www.jedec.org under Standards and Documents for alternative contact information. Published by JEDEC Solid State Technology Association 2014 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 This document may be downloaded free of charge; however JEDEC retains the copyright on this
8、material. By downloading this file the individual agrees not to charge for or resell the resulting material. PRICE: Contact JEDEC Printed in the U.S.A. All rights reserved PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by JEDEC and may not be reproduced without permission. For informatio
9、n, contact: JEDEC Solid State Technology Association 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 or refer to www.jedec.org under Standards-Documents/Copyright Information. JEDEC Standard No. 74A -i- EARLY LIFE FAILURE RATE CALCULATION PROCEDURE FOR SEMICONDUCTOR COMPONENTS Conten
10、ts Page Introduction ii 1 Scope 1 2 Reference documents 1 3 Terms and definitions 2 4 General requirements 4 4.1 Test samples 4 4.2 Test conditions 4 4.3 Test durations 4 4.4 Failure analysis 4 5 Calculation ELFR 5 5.1 Exponential distribution (constant failure rate) 8 5.1.1 Exponential distribution
11、, single ELF test 8 5.1.1.1 Exponential distribution1 failure mechanism, single ELF test 9 5.1.1.2 Exponential distribution2 failure mechanisms, single ELF test 9 5.1.2 Exponential distribution1 failure mechanism, multiple ELF tests 9 5.1.2.1 Exponential distribution1 failure mechanism, multiple ELF
12、 tests 10 5.1.3 Exponential distributionmultiple failure mechanisms, multiple ELF tests 10 5.1.3.1 Exponential distribution2 failure mechanisms, multiple ELF tests 10 5.2 Decreasing failure rate 10 5.2.1 Decreasing failure rate, single ELF test 11 5.2.1.1 Decreasing failure rate1 failure mechanism,
13、single ELF test 13 5.2.1.2 Decreasing failure rate2 failure mechanisms, single ELF test 14 5.2.2 Decreasing failure rate1 failure mechanism, multiple ELF tests 14 5.2.2.1 Decreasing failure rate1 failure mechanism, multiple ELF tests 15 5.2.3 Decreasing failure ratemultiple failure mechanisms, multi
14、ple ELF tests 15 5.2.3.1 Decreasing failure rate2 failure mechanisms, multiple ELF tests 15 5.3 Alternate ELFR calculation for multiple failure mechanisms 16 Annex A Example using the exponential distribution with 1 failure mechanism and a single ELF test 17 Annex B Example using the exponential dis
15、tribution with 2 failure mechanisms and a single ELF test 18 Annex C Example using the exponential distribution with 1 failure mechanism and 3 ELF tests 20 Annex D Example using the exponential distribution with 2 failure mechanisms and 3 ELF tests 21 Annex E Example using a Weibull distribution wit
16、h decreasing rate with 1 failure mechanism and a single ELF test 23 Annex F Example using the Weibull distribution with 2 failure mechanisms and a single ELF test 24 Annex G Example using a Weibull distribution with decreasing rate distribution with 1 failure mechanism and 3 ELF tests 26 Annex H Exa
17、mple using a Weibull distribution with decreasing rate with 2 failure mechanisms and 3 ELF tests 27 Annex J Chi Square values table 29 Annex K (informative) Differences between JESD74A and JESD74 30 Figures 5.1 Reliability bathtub curve 5 5.2 Cumulative failures versus stress time 11 Tables J.1 Squa
18、re distribution, 2 values at various confidence levels 29 JEDEC Standard No. 74A -ii- EARLY LIFE FAILURE RATE CALCULATION PROCEDURE FOR SEMICONDUCTOR COMPONENTS Introduction Early life failure rate (ELFR) measurement of a product is typically performed during product qualifications or as part of ong
19、oing product reliability monitoring activities. These tests measure reliability performance over the products first several months in the field. It is therefore important to establish a methodology that will accurately project early life failure rate to actual customer use conditions. JEDEC Standard
20、 No. 74A Page 1 EARLY LIFE FAILURE RATE CALCULATION PROCEDURE FOR SEMICONDUCTOR COMPONENTS (From JEDEC Board Ballot JCB-07-03, formulated under the cognizance of the JC-14.3 Subcommittee on Silicon Devices Reliability Qualification and monitoring.) 1 Scope This standard defines methods for calculati
21、ng the early life failure rate of a product, using accelerated testing, whose failure rate is constant or decreasing over time. For technologies where there is adequate field failure data, alternative methods may be used to establish the early life failure rate. The purpose of this standard is to de
22、fine a procedure for performing measurement and calculation of early life failure rates. Projections can be used to compare reliability performance with objectives, provide line feedback, support service cost estimates, and set product test and screen strategies to ensure that the ELFR meets custome
23、rs requirements. 2 Reference documents JESD22-A108, Temperature, Bias, and Operating Life JESD659, Failure-Mechanism-Driven Reliability Monitoring JESD47, Stress-Test-Driven Qualification of Integrated Circuits JEP122, Failure Mechanisms and Models for Silicon Semiconductor Devices JESD91, Method fo
24、r Developing Acceleration Models for Electronic Component Failure Mechanisms. JESD85, Methods for Calculating Failure Rate in Units of FIT JESD94, Application Specific Qualification Using Knowledge Based Test Methodology JEP143, Solid State Reliability Assessment Qualification Methodologies JEP148,
25、Reliability Qualification of Semiconductor Devices Based on Physics of Failure Risk and Opportunity Assessment JEDEC Standard No. 74A Page 2 3 Terms and definitions accelerated ELF test time (tA): The duration of the accelerated ELF test. acceleration factor (A): For a given failure mechanism, the r
26、atio of the time it takes for a certain fraction of the population to fail, following application of one stress or use condition, to the corresponding time at a more severe stress or use condition. acceleration factor, temperature (AT): The acceleration factor due to changes in temperature. accelera
27、tion factor, voltage (AV): The acceleration factor due to changes in voltage. apparent activation energy (Eaa): An equivalent energy value that can be inserted in the Arrehenius equation to calculate an acceleration factor applicable to changes with temperature of time-to-failure distributions. NOTE
28、 1 An apparent activation energy is often associated with a specific failure mechanism and time-to-failure distribution for calculating the acceleration factor. NOTE 2 A composite apparent activation energy is often used to calculate a single acceleration factor, for a given time-to-failure distribu
29、tion, that is equivalent to the net effect of the various thermal acceleration factors associated with multiple failure mechanisms. NOTE 3 Various physical thermal activation energies may contribute to the shape of the time-to-failure distribution. NOTE 4 The term “apparent“ is used because Eaais an
30、alogous in use to Eain the Arrhenius equation; Eaais used for a time-to-failure distribution, while Eaapplies to a chemical thermal reaction rate. bathtub curve: A plot of failure rate versus time or cycles that exhibits three phases of life: infant mortality (initially decreasing failure rate), int
31、rinsic or useful life (relatively constant failure rate), and wear-out (increasing failure rate). characteristic life (for the Weibull distribution)( ): The time at which F(t) equals (1-e-1) (63.2%) countable failure: A failure due to an inherent defect in the semiconductor component during early-li
32、fe-failure (ELF) stress tests. NOTE Failures due to electrical overstress (EOS), electrostatic discharge (ESD), mechanical damage, etc., are not counted, but the units are considered to have completed testing through the last successful readout when computing device hours. cumulative distribution fu
33、nction of the time-to-failure; cumulative mortality function F(t): The probability that a device will have failed by a specified time t1or the fraction of units that have failed by that time. NOTE 1 The value of this function is given by the integral of f(t) from 0 to t1. NOTE 2 This function is gen
34、erally expressed in percent (%) or in parts per million (ppm) for a defined early-life failure period. NOTE 3 The abbreviation CDF is often used; however, the symbol F(t) is preferred. JEDEC Standard No. 74A Page 3 3 Terms and definitions (contd) cumulative fraction failing (CFF): The total fraction
35、 failing based on the starting sample size over a given time interval. NOTE This is generally expressed in percent (%) or in ppm. early life: The customer initial use period. NOTE This period typically ranges from three months to one year of operation. early-life-failure (ELF) test: An accelerated t
36、est designed to measure the early life failure rate (ELFR), which may be experienced during the customer initial use period. NOTE The test process is specified in JESD47.early life period (tELF): The specified early life period as defined by the user or the supplier. failure rate (): The fraction of
37、 a population that fails within a specified interval, divided by that interval. NOTE The statistical upper limit estimate of the failure rate is usually calculated using the chi-squared function. failures in time (FIT): The number of failures per 109device-hours. population failure distributions: Th
38、e applicable mortality functions. NOTE Typically used failure distributions for early-life failures include the Weibull and Poisson (exponential); for useful life and wear-out and also the Gaussian (normal) and lognormal distributions are used. ppm: Parts per million. ppm/time period: The number of
39、failures per million units in the time period of interest. qualification family: Products sharing the same semiconductor process technology. signature analysis: The process of assigning the most likely failure mechanism to a countable failure based on its unique electrical failure characteristics an
40、d an established physical analysis database for that mechanism. use condition time (tU): The time interval equivalent to the ELF test duration, as determined by the product of the acceleration factor and the actual accelerated test time: A tA. JEDEC Standard No. 74A Page 4 4 General requirements 4.1
41、 Test samples ELFR testing requires, as specified in JESD47Ds Table 1 and Table A, a statistically significant sample size at a minimum 60% confidence to measure the ELFR associated with the component. The sample shall be drawn from a minimum of 3 nonconsecutive production lots, and shall be compris
42、ed of representative samples from the same qualification family. Samples from any single lot should not exceed 40% of the total sample required. All samples shall be fabricated and assembled in the same production site and with the same production process. The test vehicle should represent the highe
43、st design density available for qualification. Lower sample sizes may be used with justification (e.g., high component costs, limited supply). ELFR is required to show the process capability of each technology, process, or product family. These data are generic in nature and are generally accumulate
44、d through an internal reliability monitor program. For a new device qualification that is the first of its kind in the technology, process, or product family, it may take up to one year post-qualification to accumulate adequate statistical sampling to fulfill this requirement. 4.2 Test conditions Te
45、st samples shall be placed under stress as per applicable JEDEC test methods, e.g., JEDEC Standard JESD22-A108. Stress tests will be conducted at a voltage level, frequency, temperature, humidity, and other parameters as recommended in the JEDEC test methods. Alternative stress conditions that yield
46、 equivalent results may be used if empirically justified. 4.3 Test duration Stress test conditions shall be continuously applied for a time sufficient to represent customers early life period. The minimum duration will be dictated by the acceleration for the expected or established prevailing defect
47、 mix. Common practice stress durations are between 48 and 168 hours. Test durations outside the stipulated range may be used with empirical model justification. Determination of failure times prior to the termination of stress can be useful; either continuous monitoring via in situ testing or interi
48、m test readouts that can help bound failure times prior to the end of stress. The time of failure is the earliest readout at which a device fails one or more electrical tests per the datasheet specification. 4.4 Failure analysis It is recommended that failures will be electrically and physically ana
49、lyzed to root cause. Signature analysis may be applied. JEDEC Standard No. 74A Page 5 5 Calculating ELFR A typical time distribution for semiconductor component failures is depicted by the “bathtub” curve in Figure 5.1. The curve has three distinct regions: a rapidly decreasing “infant mortality” portion; a stable, useful life portion where the failure rate continues to decrease or is essentially constant; and a period of increasing failure rate representing the onset of wear-out. Infant mortality and useful life failures are caused by de
copyright@ 2008-2019 麦多课文库（www.mydoc123.com）网站版权所有
备案/许可证编号：苏ICP备17064731号-1