JEDEC JESD75-1999 Ball Grid Array Pinouts Standardized for 32-Bit Logic Functions《32位逻辑功能的球状网络阵列插脚引线标准化》.pdf

1、JEDECSTANDARDBall Grid Array Pinouts Standardizedfor 32-Bit Logic FunctionsJESD75NOVEMBER 1999ELECTRONIC INDUSTRIES ALLIANCEJEDEC Solid State Technology AssociationNOTICEEIA/JEDEC standards and publications contain material that has been prepared, reviewed, andapproved through the JEDEC Board of Dir

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7、n, VA 22201-3834, (703)907-7560/7559 or www.jedec.orgPublished by ELECTRONIC INDUSTRIES ALLIANCE 19992500 Wilson BoulevardArlington, VA 22201-3834This document may be downloaded free of charge, however EIA retains thecopyright on this material. By downloading this file the individual agrees not toch

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10、oulevardArlington, Virginia 22201-3834or call (703) 907-7559JEDEC Standard No. 75Page 1BALL GRID ARRAY PINOUTS STANDARDIZED FOR 32-BIT LOGIC FUNCTIONS(Formerly JEDEC Board Ballot JCB-99-51, formulated under the cognizance of the JC-40 Committee on Digital Logic.)1 Background1.1 PurposeTo provide a p

11、inout standard for dual-die 32-bit logic devices offered in a 96- and 114-ball grid array package for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.1.2 ScopeThis standard defines device pinout for 32-bit wide buffer, driver and transceiv

12、er functions. This pinout specifically applies to the conversion of DIP-packaged 16-bit logic devices to LFBGA-packaged dual-die 32-bit logic devices. 2 Definitions for the purpose of this document2.1 DefinitionsDIP: Dual In-line Pin Package (gull-wing)LFBGA:Low-Profile Fine-Pitch Ball Grid Array (M

13、O-205)SSOP:Shrink Small-Outline Package; 0.25“ lead pitch; 0.3“ wide body (MO-118)TSSOP:Thin Shrink Small-Outline Package; 0.5-mm lead pitch; 6.4-mm wide body (MO-153)TVSOP:Thin Very Small-Outline Package; 0.4-mm lead pitch; 4.4-mm wide body (MO-194)3 Pinout standard3.1 DescriptionThe following crit

14、eria shall be used to convert existing 16-bit logic device functions offered in 48- and 56-pin DIP packages (SSOP, TSSOP, TVSOP) to 32-bit logic device functions offered in 96- and 114-ball LFBGA packages:A.Attributes for the LFBGA packages shall be as follows:(1)96-Ball, 0.8-mm ball pitch with 5.5-

15、mm 13.5-mm body size and 6-row 16-column ball matrix, or the(2)114-Ball, 0.8-mm ball pitch with 5.5-mm 16.0-mm body size and 6-row 19-column ball matrix.B.Device conversion shall be as follows:C.The pinout conversions shall be in accordance with the diagrams shown in section 3.3 and 3.6.DIP package

16、LFBGA package48-pin 96-ball56-pin 114-ballJEDEC Standard No. 75Page 23.2 96-ball LFBGA (MO-205CC)Figure 1. Pinout configuration3.3 Pin conversion for 96-ball LFBGAThe pin conversion adopts the naming convention of logic devices in 48-pin packages (e.g. SSOP, TSSOP, TVSOP).Figure 2. Pin conversion to

17、p view3.4 Pin assignment for 96-ball LFBGAGND: B3, B4, D3, D4, E3, E4, G3, G4, K3, K4, M3, M4, N3, N4, R3, and R4VDD: C3, C4, F3, F4, L3, L4, P3, and P4Control: A3, A4, H3, H4, J3, J4, T3, and T4I/O and Signals: all Row-1, -2, -5 and -6 pins.6A46A43A40A37A35A32A29A27B46B43B40B37B35B32B29B275A47A44A4

18、1A38A36A33A30A26B47B44B41B38B36B33B30B264A48A45A42A39A34A31A28A25B48B45B42B39B34B31B28B253A1A4A7A10A15A18A21A24B1B4B7B10B15B18B21B242A2A5A8A11A13A16A19A23B2B5B8B11B13B16B19B231A3A6A9A12A14A17A20A22B3B6B9B12B14B17B20B22ABCDEFGHJKLMNPRTTOP VIEWJHGFEDCBA213465PNMLK TRJEDEC Standard No. 75Page 33.5 114-

19、ball LFBGA (MO-205DC)Figure 3. Pinout configuration3.6 3.6 Pin conversion for 114-ball LFBGAThe pin conversion adopts the naming convention of logic devices in 56-pin packages (e.g. SSOP, TSSOP, TVSOP).Figure 4. Pin conversion top viewGND Pins: C3, C4, E3, E4, F3, F4, H3, H4, M3, M4, P3, P4, R3, R4,

20、 U3, and U4VDDPins: D3, D4, G3, G4, N3, N4, T3, and T4Control Pins: A2, A3, A4, A5, B3, J2, J3, J4, J5, K2, K3, K5, L2, L3, L5, V3, V4, W2, W3, and W5GND or Control Pins: B4, K4, L4, and W4#I/O Pins: A1, A6, B1, B2, B5, B6, C1, C2, C5, C6, D1, D2, D5, D6, E1, E2 ,E5 ,E6, F1, F2, F5, F6, G1, G2, G5,

21、G6, H1, H2, H5, H6, J1, J6, L1, L6, M1, M2, M5, M6, N1, N2, N5, N6, P1, P2, P5, P6, R1, R2, R5, R6, T1, T2, T5, T6, U1, U2, U5, U6, V1, V2, V5, V6, W1, and W6*No Connection Pins: K1 and K64 Reference to other applicable JEDEC standards and publicationsJEP95: JEDEC Registered and Standard Outlines fo

22、r Solid State and Related Products6A52#A49#A47#A44#A42#A40#A37#A36#A33#NC*B52#B49#B47#B44#B42#B40#B37#B36#B33#5A54A51#A48#A45#A43#A41#A38#A34#A31B55B54B51#B48#B45#B43#B41#B38#B34#B314A55A56A53A50A46A39A35A32A30A29B56B53B50B46B39B35B32B30B293A2A1A4A7A11A18A22A25A27A28B1B4B7B11B18B22B25B27B282A3A6#A9#A12#A14#A16#A19#A23#A26B2B3B6#B9#B12#B14#B16#B19#B23#B261A5#A8#A10#A13#A15#A17#A20#A21#A24#NC*B5#B8#B10#B13#B15#B17#B20#B21#B24#ABCDE FGH J KLMNPRTUVWTOP VIEWJHGFEDCBA213465PNMLK TR U WV