JEDEC JESD79-4-1-2017 3D Stacked DRAM (Addendum No 1 to JESD79-4).pdf

1、FEBRUARY 2017Addendum No. 1 to JESD79-4, JEDECSTANDARDJEDEC SOLID STATE TECHNOLOGY ASSOCIATIONJESD79-4-13D Stacked DRAM NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors level and subsequently reviewed and app

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8、lting material. PRICE: Contact JEDEC Printed in the U.S.A. All rights reserved PLEASE!DONT VIOLATETHELAW!This document is copyrighted by JEDEC and may not bereproduced without permission.For information, contact:JEDEC Solid State Technology Association3103 North 10th StreetSuite 240 SouthArlington,

9、VA 22201-2107or refer to www.jedec.org under Standards-Documents/Copyright Information.JEDEC Standard No. 79-4-1-i-ADDENDUM No. 1 to JESD79-4, 3D STACKED SDRAMContents1 Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10、 . . . . . . . . 12 3DS SDRAM Package Pinout and Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2 Pinou

11、t Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.3 3D Stacked / DDR4 SDRAM x4 Ballout using MO-207 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.4 3D Stacked / DDR4 SDRAM x8 Ballout using M

12、O-207 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32.5 Logical Rank Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42.6 3D Stack Organizations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13、 . . . . . . . . . . . . . . . . . . . . . . . . . . 42.7 3DS SDRAM System Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42.8 DDR4 3DS Stack Addressing Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14、 . . . . . . . 52.9 Logical Rank, Bank Group and Bank Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103.1 Simplified S

15、tate Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103.2 Basic Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103.3 Reset Signal and Initiali

16、zation Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103.4 Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 SDRAM Command Description and Operation . . . . . .

17、. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154.1 ACTIVATE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154.2 Precharge and Precharge All Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . .

18、. . . . . . . . . . . . . . . 164.3 Read and Write Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174.4 Refresh Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

19、. . . . 194.5 Self-Refresh Operation and Power-Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204.6 Write Leveling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214.7 ZQ Calibration Co

20、mmands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214.8 Command Address Parity (CA Parity) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224.9 Target Row Refresh (TRR) . . . . . . . . . . . .

21、 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234.10 Post Package Repair (PPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 On Die Termination . . . . . . . . . . . . . . . . . . . . . . . . . . .

22、 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 AC and DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

23、 . . . . . . . . . . . . . . . 238 AC and DC Output Measurement Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 Speed Bins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

24、. . 249.1 Standard 3DS Speed Bins for x4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249.2 Standard 3DS Speed Bins for x8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299.3 Notes to Speed Bin T

25、ables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3010 IDDCurrent Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3110.1 IDD, IPP, and IDDQMeasurement Condition

26、s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3110.2 IDDand IPPSpecifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5011 Input/Output Capacitance . . . . . . . . . . . . . . . . . . . . . . . .

27、. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5312 Electrical Characteristics and AC Timings for DDR4-1600-3DS to DDR4-2400-3DS . . . . . . . 5412.1 Refresh parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

28、. . 5412.2 Timing Parameters by Speed Grade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55JEDEC Standard No. 79-4-1-ii-JEDEC Standard No. 79-4-1Page 1ADDENDUM No. 1 to JESD79-4, 3D STACKED SDRAM(From JEDEC Board Ballot JCB-16-29, formulated under the

29、 cognizance of the JC-42.3C Subcommittee on DRAM Parametrics.)1ScopeThis document defines the 3DS DDR4 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of require

30、ments for a compliant 8 Gbit through 128 Gbit for x4, x8 3DS DDR4 SDRAM devices. This addendum was created based on the JESD79-4 DDR4 SDRAM specification. Each aspect of the changes for 3DS DDR4 SDRAM operation was considered. Any TBDs, as of the publication of this document, are under discussion by

31、 the formulating committee. The requirement for 3DS devices compliant to this spec addendum is to have a single electrical load for the stacked devices no matter if the stack is comprised of 2, 4 or 8 devices. The I/O buffer circuitry can be built into the base SDRAM of the stack or into a separate

32、logic buffer device. In either case (built in native circuitry or separate logic die), the assumption is that the I/O buffers are located at the bottom of the stack closest to the package substrate. All pictures and diagrams in the spec depict a master die at the bottom of the stack; it is associate

33、d with logical rank 0.2 3DS SDRAM Package Pinout and Addressing2.1 OverviewThese ballouts have been derived from JESD79-4. The ballout comprehends x4 and x8 data widths, where x4 is a subset of the x8 ballout, and the addressing described in this section.2.2 Pinout DescriptionThe following table onl

34、y documents differences of DDR4 3DS SDRAMs relative to the pinout description in JESD79-4.Symbol Type FunctionPAR InputCommand and Address Parity Input : DDR4 Supports Even Parity check in DRAMs with MR setting. Once its enabled via Register in MR5, then DRAM calculates Parity with ACT_n,RAS_n/A16,C

35、AS_n/A15,WE_n/A14,BG0-BG1,BA0-BA1,A17-A0 and C0, C1, C2. Input parity should maintain at the rising edge of the clock and at the same time with command and address with CS_n LOWNOTE 1 Input only pins (BG0-BG1,BA0-BA1, A0-A17, ACT_n, RAS_n/A16, CAS_n/A15, WE_n/A14, CS_n, CKE, ODT, C0, C1, C2 and RESE

36、T_n) do not supply termination.JEDEC Standard No. 79-4-1Page 22.3 3D Stacked / DDR4 SDRAM x4 Ballout using MO-207Ball locations in Figure 1, “3D Stacked DDR4 SDRAM x4 Ballout” show the proposed DDR4 3D Stacked SDRAM x4 ballout.X-ray view from package top surface1 2 3 4 5 6 7 8 9NC NC NC NC NC NCNC N

37、C NC NC NC NCA NC VDD VSSQ NC NC VSSQ VSS NCB VPP VDDQ DQS_c DQ1 VDDQ ZQC VDDQ DQ0 DQS_t VDD VSS VDDQD VSSQ NC DQ2 DQ3 NC VSSQE VSS VDDQ NC NC VDDQ VSSF VDD C2, NC11.This pin is not connected for 3DS devices with two or four logical ranks.ODT CK_t CK_c VDDG VSS C0 CKE CS_n C1, NC22.This pin is not c

38、onnected for 3DS devices with two logical ranks.RFUH VDD WE_n, A14 ACT_n CAS_n, A15 RAS_n, A16 VSSJ VREFCA BG0 A10, AP A12, BC_n BG1 VDDK VSS BA0 A4 A3 BA1 VSSL RESET_n A6 A0 A1 A5 ALERT_nM VDD A8 A2 A9 A7 VPPN NC VSS A11 PAR A17, NC33.This pin is not connected for 4Gb and 8Gb devices., A13 VDD NCNC

39、 NC NC NC NC NCNC NC NC NC NC NCFigure 1 3D Stacked DDR4 SDRAM x4 BalloutJEDEC Standard No. 79-4-1Page 32.4 3D Stacked / DDR4 SDRAM x8 Ballout using MO-207Ball locations in Figure 2, “3D Stacked DDR4 SDRAM x8 Ballout” show the proposed DDR4 3D Stacked SDRAM x8 ballout.X-ray view from package top sur

40、face1 2 3 4 5 6 7 8 9NC NC NC NC NC NCNC NC NC NC NC NCA NC VDD VSSQ TDQS_cDBI_n, TDQS_t VSSQ VSS NCB VPP VDDQ DQS_c DQ1 VDDQ ZQC VDDQ DQ0 DQS_t VDD VSS VDDQD VSSQ DQ4 DQ2 DQ3 DQ5 VSSQE VSS VDDQ DQ6 DQ7 VDDQ VSSF VDD C2, NC11.This pin is not connected for 3DS devices with two or four logical ranks.O

41、DT CK_t CK_c VDDG VSS C0 CKE CS_n C1, NC22.This pin is not connected for 3DS devices with two logical ranks.RFUH VDD WE_n, A14 ACT_n CAS_n, A15 RAS_n, A16 VSSJ VREFCA BG0 A10, AP A12, BC_n BG1 VDDK VSS BA0 A4 A3 BA1 VSSL RESET_n A6 A0 A1 A5 ALERT_nM VDD A8 A2 A9 A7 VPPN NC VSS A11 PAR NC A13 VDD NCN

42、C NC NC NC NC NCNC NC NC NC NC NCFigure 2 3D Stacked DDR4 SDRAM x8 BalloutJEDEC Standard No. 79-4-1Page 42.5 Logical Rank AddressingThe 3DS package is organized into two, four or eight logical ranks.For DDR4 3DS devices, the logical ranks are selected by the Chip ID bus C2:0.The functional behavior

43、of logical rank(s) should not deviate from monolithic DDR4 SDRAMs (specified in JESD79-4A), except when noted in this document. Each logical rank may be implemented as a single slice but the DDR4 3DS addendum doesnt require this to be the case.2.6 3D Stack OrganizationsTable 1, “Supported 3D Stack O

44、rganizations,” indicates valid configurations supported by the DDR4 3DS addendum.Table 1 Supported 3D Stack OrganizationsLogical Ranks# of CS_n Chip ID # of CKE # of ODT2 1 C0 1 14 1 C0, C1 1 18 1 C0, C1, C2 1 1Figure 3, Figure 4, and Figure 5 show one architectural diagram per row of Table 1. For t

45、he names of the these figures the standard 3DS configuration notation LR-CS-CKE-ODT is used where LR indicates the number of logical ranks, CS_n indicates the number of chip select inputs, CKE indicates the number of CKE inputs and ODT indicates the number of ODT inputs. Since there is only one vali

46、d configuration for each number of logical ranks, this document will typical use the abbreviations 2H, 4H and 8H to describe 3DS devices with two, four or eight logical ranks.2.7 3DS SDRAM System Addressing3DS addressing scheme for DDR4 3DS devices is explained in section 2.8. This document comprehe

47、nds using these 3DS devices in RDIMM and LRDIMM applications with x4 or x8 3DS SDRAMs.JEDEC Standard No. 79-4-1Page 52.8 DDR4 3DS Stack Addressing TableTable 2, Table 3 and Table 4 indicate the address and select pins that are used for different configurations of 3DS stacks. The DDR4 3DS devices may

48、 be derived from monolithic DDR4 devices. Therefore the address signals used within a logical rank are identical to the address signals used by a monolithic DRAM of the same density. Logical Rank 0 is considered to be associated with the master die.Figure 3 2-1-1-1 Device (2H)Table 2 DDR4 Address Ta

49、ble: 2H Stacked SDRAMDDR4 3DS Address Table: 2H 3D Stacked SDRAM3DS Logical Rank Organization 3DS Package OrganizationDensityx4 Page Sizex8 Page SizeMSB AddressCapacityLogical RankCS_n C0ColRowx4 Die x8 Die4 Gb 512 B 1 KB A9 A15 A14 8 Gb0 L L1 L H8 Gb 512 B 1 KB A9 A16 A15 16 Gb0 L L1 L H16 Gb 512 B 1 KB A9 A17 A16 32 Gb0 L L1 L HJEDEC Standard No. 79-4-1Page 62.8 DDR4 3DS Stack Addressing Table (contd)Figure 4 4-1-1-1 Device (4H)Table 3 DDR4 Address Table: 4H Stacked SDRAMDDR4 3DS Address Table: 4H 3D Stacked SDRAM3DS Logical Rank Organization 3DS Package Organizat