JEDEC JESD79-4A-2013 DDR4 SDRAM.pdf

1、JEDEC SOLID STATE TECHNOLOGY ASSOCIATIONNOVEMBER 2013JEDECSTANDARDDDR4 SDRAMJESD79-4A(Revision of JESD79-4, September 2012)NOTICEJEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors level and subsequently reviewed and a

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9、01-2107or call (703) 907-7559JEDEC Standard No. 79-4A 1. Scope 12. DDR4 SDRAM Package Pinout and Addressing 22.1 DDR4 SDRAM Row for X4,X8 and X16 . 22.2 DDR4 SDRAM Ball Pitch. 22.3 DDR4 SDRAM Columns for X4,X8 and X16 . 22.4 DDR4 SDRAM X4/8 Ballout using MO-207 22.5 DDR4 SDRAM X16 Ballout using MO-2

10、07 32.6 Pinout Description 52.7 DDR4 SDRAM Addressing 73. Functional Description 83.1 Simplified State Diagram . 83.2 Basic Functionality. 93.3 RESET and Initialization Procedure 93.3.1 Power-up Initialization Sequence 93.3.2 Reset Initialization with Stable Power . 113.4 Register Definition . 123.4

11、.1 Programming the mode registers 123.5 Mode Register . 134. DDR4 SDRAM Command Description and Operation 244.1 Command Truth Table . 244.2 CKE Truth Table. 254.3 Burst Length, Type and Order . 264.3.1 BL8 Burst order with CRC Enabled 264.4 DLL-off Mode Clock to Data Strobe relationship 854.24.1.2 R

12、EAD Timing; Data Strobe to Data relationship 864.24.1.3 tLZ(DQS), tLZ(DQ), tHZ(DQS), tHZ(DQ) Calculation 874.24.1.4 tRPRE Calculation 884.24.1.5 tRPST Calculation 894.24.2 READ Burst Operation 904.24.3 Burst Read Operation followed by a Precharge 1014.24.4 Burst Read Operation with Read DBI (Data Bu

13、s Inversion) 1034.24.5 Burst Read Operation with Command/Address Parity 1044.24.6 Read to Write with Write CRC . 1054.24.7 Read to Read with CS to CA Latency . 1064.25 Write Operation 1074.25.1 Write Burst Operation 1074.26 Refresh Command. 1234.27 Self refresh Operation 1244.27.1 Low Power Auto Sel

14、f Refresh . 1264.28 Power down Mode . 1274.28.1 Power-Down Entry and Exit 1274.28.2 Power-Down clarifications . 1324.29 Maximum Power Saving Mode 1324.29.1 Maximum power saving mode. 1324.29.2 Mode entry 1324.29.3 CKE transition during the mode 1334.29.4 Mode exit . 1344.29.5 Timing parameter bin of

15、 Maximum Power Saving Mode for DDR4-1600/1866/2133/2400/2666/3200 1344.30 Connectivity Test Mode 1354.30.1 Introduction 1354.30.2 Pin Mapping 1354.30.3 Logic Equations . 1364.30.3.1 Min Term Equations .136-ii-JEDEC Standard No. 79-4A 4.30.3.2 Output equations for x16 devices 1364.30.3.3 Output equat

16、ions for x8 devices 1364.30.3.4 Output equations for x4 devices 1364.30.4 Timing Requirement 1374.31 CLK to Read DQS timing parameters 1375. On-Die Termination . 1395.1 ODT Mode Register and ODT State Table. 1395.2 Synchronous ODT Mode 1415.2.1 ODT Latency and Posted ODT . 1425.2.2 Timing Parameters

17、 1425.2.3 ODT during Reads: . 1435.3 Dynamic ODT. 1445.3.1 Functional Description . 1445.3.2 ODT Timing Diagrams . 1455.4 Asynchronous ODT mode 1465.5 ODT buffer disabled mode for Power down. 1475.6 ODT Timing Definitions 1485.6.1 Test Load for ODT Timings . 1485.6.2 ODT Timing Definitions . 1486. A

18、bsolute Maximum Ratings . 1507. AC LOW: no Autoprecharge).A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by bank addresses. A12 / BC_n InputBurst Chop: A12

19、/ BC_n is sampled during Read and Write commands to determine if burst chop (on-the-fly) will be performed. (HIGH, no burst chop; LOW: burst chopped). See command truth table for details.RESET_n InputActive Low Asynchronous Reset: Reset is active when RESET_n is LOW, and inactive when RESET_n is HIG

20、H. RESET_n must be HIGH during normal operation. RESET_n is a CMOS rail to rail signal with DC high and low at 80% and 20% of VDD, JEDEC Standard No. 79-4APage 6DQ Input / OutputData Input/ Output: Bi-directional data bus. If CRC is enabled via Mode register then CRC code is added at the end of Data

21、 Burst. Any DQ from DQ0DQ3 may indicate the internal Vref level during test via Mode Register Setting MR4 A4=High. Refer to vendor specific data sheets to determine which DQ is used.DQS_t, DQS_c, DQSU_t, DQSU_c, DQSL_t, DQSL_cInput / OutputData Strobe: output with read data, input with write data. E

22、dge-aligned with read data, centered in write data. For the x16, DQSL corresponds to the data on DQL0-DQL7; DQSU corresponds to the data on DQU0-DQU7. The data strobe DQS_t, DQSL_t and DQSU_t are paired with differential signals DQS_c, DQSL_c, and DQSU_c, respectively, to provide differential pair s

23、ignaling to the system during reads and writes. DDR4 SDRAM supports differential data strobe only and does not support single-ended.TDQS_t, TDQS_c OutputTermination Data Strobe: TDQS_t/TDQS_c is applicable for x8 DRAMs only. When enabled via Mode Register A11 = 1 in MR1, the DRAM will enable the sam

24、e termination resistance function on TDQS_t/TDQS_c that is applied to DQS_t/DQS_c. When disabled via mode register A11 = 0 in MR1, DM/DBI/TDQS will provide the data mask function or Data Bus Inversion depending on MR5; A11,12,10and TDQS_c is not used. x4/x16 DRAMs must disable the TDQS function via

25、mode register A11 = 0 in MR1.PAR InputCommand and Address Parity Input: DDR4 Supports Even Parity check in DRAMs with MR setting. Once its enabled via Register in MR5, then DRAM calculates Parity with ACT_n,RAS_n/A16,CAS_n/A15,WE_n/A14,BG0-BG1,BA0-BA1,A17-A0. Input parity should maintain at the risi

26、ng edge of the clock and at the same time with command BA0-BA1 select the bank; A0-A17 select the row; refer to “DDR4 SDRAM Addressing” on Section 2.7 for specific requirements). The address bits registered coincident with the Read or Write command are used to select the starting column location for

27、 the burst operation, determine if the auto precharge command is to be issued (via A10), and select BC4 or BL8 mode on the fly (via A12) if enabled in the mode register.Prior to normal operation, the DDR4 SDRAM must be powered up and initialized in a predefined manner.The following sections provide

28、detailed information covering device reset and initialization, register definition, command descriptions,and device operation.3.3 RESET and Initialization Procedure For power-up and reset initialization, in order to prevent DRAM from functioning improperly default values for the following MR setting

29、s need to be defined.Gear down mode (MR3 A3): 0 = 1/2 RatePer DRAM Addressability (MR3 A4): 0 = DisableMax Power Saving Mode (MR4 A1): 0 = DisableCS to Command/Address Latency (MR4 A8:6): 000 = DisableCA Parity Latency Mode (MR5 A2:0): 000 = Disable3.3.1 Power-up Initialization SequenceThe following

30、 sequence is required for POWER UP and Initialization and is shown in Figure 3.1. Apply power (RESET_n is recommended to be maintained below 0.2 x VDD; all other inputs may be undefined). RESET_n needsto be maintained for minimum 200us with stable power. CKE is pulled “L” anytime before RESET_n bein

31、g de-asserted (min. time10ns). The power voltage ramp time between 300mV to VDDmin must be no greater than 200ms; and during the ramp, VDD VDDQand (VDD-VDDQ) Write Command Latency when CRC and DM are both enabledAddress Operating Mode DescriptionBG1 RFU 0 = must be programmed to 0 during MRSBG0, BA1

32、:BA0 MR Select000 = MR0 100 = MR4001 = MR1 101 = MR5010 = MR2 110 = MR6011 = MR3 111 = RCW1A17 RFU 0 = must be programmed to 0 during MRSA13 RFU 0 = must be programmed to 0 during MRSA12:A11 MPR Read Format00 = Serial 10 = Staggered01 = Parallel 11 = Reserved TemperatureA10:A9Write CMD Latency when

33、CRC and DM are enabled(see Table 8)A8:A6Fine Granularity Refresh Mode(see Table 7)A5 Temperature sensor readout 0 : disabled 1: enabledA4 Per DRAM Addressability 0 = Disable 1 = EnableA3 Geardown Mode 0 = 1/2 Rate 1 = 1/4 RateA2 MPR Operation 0 = Normal 1 = Dataflow from/to MPRA1:A0 MPR page Selecti

34、on00 = Page0 10 = Page201 = Page1 11 = Page3(see Table.8)A8 A7 A6Fine Granularity Refresh0 0 0 Normal (Fixed 1x)0 0 1 Fixed 2x0 1 0 Fixed 4x0 1 1 Reserved1 0 0 Reserved1 0 1 Enable on the fly 2x1 1 0 Enable on the fly 4x1 1 1 ReservedA10 A9CRC+DM Write Command Latency Speed Bin 0 0 4nCK 16000 1 5nCK

35、 1866,2133,24001 0 6nCK TBD1 1 RFU RFUJEDEC Standard No. 79-4APage 18Table 9 MPR Data FormatMPR page0 (Training Pattern)MPR page1 (CA Parity Error Log)NOTE 1 MPR used for C/A parity error log readout is enabled by setting A2 in MR3NOTE 2 For higher density of DRAM, where A17 is not used, MPR21 shoul

36、d be treated as dont care.NOTE 3 If a device is used in monolithic application, where C2:0 are not used, then MPR32:0 should be treated as dont care.NOTE 4 MPR3 bit 02 (CA parity latency) reflects the latest programmed CA parity latency values.Address MPR Location 7 6 5 4 3 2 1 0 noteBA1:BA000 = MPR

37、0 0 1 0 1 0 1 0 1 Read/Write (default value)01 = MPR1 0 0 1 1 0 0 1 110 = MPR2 0 0 0 0 1 1 1 111 = MPR3 0 0 0 0 0 0 0 0Address MPR Location 7 6 5 4 3 2 1 0 noteBA1:BA000 = MPR0 A7 A6 A5 A4 A3 A2 A1 A0Read-only01 = MPR1 CAS_n/A15WE_n/A14A13 A12 A11 A10 A9 A810 = MPR2 PAR ACT_n BG1 BG0 BA1 BA0 A17 RAS

38、_n/A1611 = MPR3 CRC Error StatusCA Par-ity Error StatusCA Parity Latency4C2 C1 C0MR5.A2 MR5.A1 MR5.A0JEDEC Standard No. 79-4A Page 19MPR page2 (MRS Readout)MR bit for TemperatureMR3 bit A5=1 : DRAM updates the temperature sensor status to MPR Page 2 (MPR0 bits A4:A3). Temperature data is guaranteed

39、bythe DRAM to be no more than 32ms old at the time of MPR Read of the Temperature Sensor Status bits.MR3 bit A5=0: DRAM disables updates to the temperature sensor status in MPR Page 2(MPR0-bit A4:A3)MPR page3 (Vendor use only)1NOTE 1 MPR page3 is specifically assigned to DRAM. Actual encoding method

40、 is vendor specific.Address MPR Location 7 6 5 4 3 2 1 0 noteBA1:BA000 = MPR0RFU RFU RFU Temperature Sen-sor Status(Table1)CRC Write EnableRtt_WRread-only- - - - - MR2 MR2- - - - - A12 A10 A901= MPR1Vref DQ Trng rangeVref DQ training ValueGear-down EnableMR6 MR6A6 A5 A4 A3 A2 A1 A0 A310 = MPR2CAS La

41、tency RFU CAS Write LatencyMR0 - MR2A6 A5 A4 A2 - A5 A4 A311 = MPR3Rtt_Nom Rtt_Park Driver ImpedanceMR1 MR5 MR2A10 A9 A6 A8 A7 A6 A2 A1MPR0 bit A4 MPR0 bit A3 Refresh Rate Range0 0 Sub 1X refresh ( tREFI)0 1 1X refresh rate(= tREFI)1 0 2X refresh rate(1/2* tREFI)1 1 rsvdAddress MPR Location 7 6 5 4

42、3 2 1 0 noteBA1:BA000 = MPR0 dont caredont caredont caredont caredont caredont caredont caredont careRead-only01 = MPR1 dont caredont caredont caredont caredont caredont caredont caredont care10 = MPR2 dont caredont caredont caredont caredont caredont caredont caredont care11 = MPR3 dont caredont ca

43、redont caredont caredont caredont caredont caredont careJEDEC Standard No. 79-4APage 20MR4NOTE 1 Reserved for Register control word setting DRAM ignores MR command with BG0,BA1;BA0=111 and doesnt respond. When RFU MR code setting is inputted, DRAM operation is not defined.Table 10 CS to CMD / ADDR L

44、atency Mode SettingAddress Operating Mode DescriptionBG1 RFU 0 = must be programmed to 0 during MRSBG0, BA1:BA0 MR Select000 = MR0 100 = MR4001 = MR1 101 = MR5010 = MR2 110 = MR6011 = MR3 111 = RCW1A17 RFU 0 = must be programmed to 0 during MRSA13 RFU 0 = must be programmed to 0 during MRSA12 Write

45、Preamble 0 = 1 nCK 1 = 2 nCKA11 Read Preamble 0 = 1 nCK 1 = 2 nCKA10Read Preamble Training Mode0 = Disable 1 = EnableA9 Self Refresh Abort 0 = Disable 1 = EnableA8:A6CS to CMD/ADDR Latency Mode (cycles)000 = Disable 100 = 6001 = 3 101 = 8010 = 4 110 = Reserved011 = 5 111 = Reserved(See Table 10)A5 R

46、FU 0 = must be programmed to 0 during MRSA4 Internal Vref Monitor 0 = Disable 1 = EnableA3Temperature Controlled Refresh Mode0 = Disable 1 = EnableA2Temperature Controlled Refresh Range0 = Normal 1 = ExtendedA1Maximum Power Down Mode0 = Disable 1 = EnableA0 RFU 0 = must be programmed to 0 during MRS

47、A8 A7 A6 CAL0 0 0 Disable00 1 301 0 41 510 0 61 81 1 0 Reserved1 1 1 ReservedJEDEC Standard No. 79-4A Page 21MR5NOTE 1 Reserved for Register control word setting .DRAM ignores MR command with BG0,BA1;BA0=111 and doesnt respond. When RFU MR code setting is inputted, DRAM operation is not defined.NOTE

48、 2 When RTT_NOM Disable is set in MR1, A5 of MR5 will be ignored.Table 11 RTT_PARKTable 12 C/A Parity Latency Mode NOTE 1 Parity latency must be programmed according to timing parameters by speed grade table Address Operating Mode DescriptionBG1 RFU 0 = must be programmed to 0 during MRSBG0, BA1:BA0

49、 MR Select 000 = MR0 100 = MR4001 = MR1 101 = MR5010 = MR2 110 = MR6011 = MR3 111 = RCW1A17 RFU 0 = must be programmed to 0 during MRSA13 RFU 0 = must be programmed to 0 during MRSA12 Read DBI 0 = Disable 1 = EnableA11 Write DBI 0 = Disable 1 = EnableA10 Data Mask 0 = Disable 1 = EnableA9 CA parity Persistent Error 0 = Disable1 = EnableA8:A6 RTT_PARK (see Table 11)A5 OD