JEDEC JESD8-13-2001 Scalable Low-Voltage Signalling for 400 mV (SLVS-400)《400mV的短系列终止逻辑(SLVS-400)》.pdf

1、JEDEC STANDARD Scalable Low-Voltage Signaling for 400 rnV (SLVS-400) JESDS-13 OCTOBER 2001 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Council level and subsequently reviewed and ap

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7、hed by O JEDEC Solid State Technology Association 2001 2500 Wilson Boulevard Arlington, VA 22201-3834 This documentmay be downloaded free of charge, however JEDEC retains the copyright on this material. By downloading this file the individual agrees not to charge for or resell the resulting material

8、. Price: Please refer to the current Catalog of JEDEC Engineering Standards and Publications or call Global Engineering Documents, USA and Canada (1-800-854-7179), International (303-397-7956) Printed in the U.S.A. All rights reserved JEDEC Standard No. 8- 13 Introduction SLVS is a chip-to-chip sign

9、aling protocol which is designed from the beginning for maximum performance and minimum power consumption. It derives from four fundamental principles: a) Maximum performance requires that both near- and far-end reflection coefficients be minimized. Therefore both driver and terminator impedances mu

10、st closely match the line impedance. b) For reasonable power consumption, signal swing should be as small as is consistent with receiver performance. c) Power supply voltages will continue to decrease, as will the swing needed for receiver performance. Therefore, the signaling protocol should be as

11、independent of the positive supply as possible. d) Additional low-impedance supplies, especially ones that can both sink and source current, are expensive both in cost and performance impact. Item (a) demands shunt termination. (c) and (d) rule out the positive signal supply and any third supply, wh

12、ich leaves ground as the termination potential. Combined with (a) this demands a signal swing between ground and 50% of the output supply, which is consistent with (c). As an added benefit, this simplifies CMOS differential receivers because they dont need to combine N- and P-channel differential in

13、puts. (b) suggests VO operation below the core-logic supply potential, which minimizes intergenerational incompatibility. Higher-level data organization is outside of the scope of this specification, but it should be noted that variations in supply and ground current are incompatibile with maximum p

14、erformance. For that reason, SLVS-400 is intended for use with DC-balanced data groupings such as 4B/6B and differential (1 B/2B) codes. Specific applications are also outside of this specifications scope. That said, it should be noted that ground termination greatly simplifies hot-insertion systems

15、. It should also be noted that with a timing budget relaxed to account for line settling and L di/dt drops the source-impedance matching of SLVS-400 allows its use in unterminated (reflected-wave) switching environments. -1- JEDEC Standard No. 8-13 -11- JEDEC Standard No. 8- 13 Page 1 SCALABLE LOW-V

16、OLTAGE SIGNALING FOR 400 MV (SLVS-400) (From JEDEC Board ballot JCB-O 1-83, formulated under the cognizance of the JC- 16 Committee on Interface Technology.) 1 Scope This standard defiies the input, output, and termination specifications for differential signaling in the SLVS-400 environment, nomina

17、lly between O and 400 mV. Power supplies other than the nominal 800 mV power for the SLVS interface are not specified. 2 Description SLVS-400 is a differential voltage-based signaling protocol. The nominal VOL of O (ground) and a nominal VOH of 400 mV. Because the driver impedance must be matched to

18、 the line and termination impedances, this requires a nominal 800 mV power supply (VDDQ). SLVS defines three primitive types: drivers, receivers, and terminators. A practical SLVS system must have at least one of each type, although it is possible and in fact quite practical for all three to be inco

19、rporated into a single node. 2.1 Drivers An SLVS-400 driver is defined to be in one of three states: High Impedance Low High Self-explanatory. Between VO(MIN) and VO(MAX) the absolute magnitude of the device current is less than or equal to IL(max, Output Thevenin potential is VSSQ; ouptut Thevenin

20、impedance is linear and within 10% of Zo around the operating point of O V. Output Thevenin potential is VDDQ; output Thevenin impedance is linear and within 20% of Zo around the operating point of vDDO/2. JEDEC Standard No. 8-13 Page 2 VDDQ 2 Description (contd) 2.2 Receivers An SLVS-400 receiver i

21、s defined to be in one of five states: Minimum Maximum Units 750 850 mV Switching High Holding High Undefined Holding Low Switching Low D,+ - D,- 2 VIH(AC) causes the receiver to switch TRUE with specified AC timings. D,+ - D,- 2 VIH(DC) guarantees that a TRUE receiver will not switch FALSE. All bet

22、s are off. D,+ - D,- I VIL(DC) guarantees that a FALSE receiver will not switch TRUE. D,+ - D,- I VIL(Ac) causes the receiver to switch FALSE with specified AC timings. 2.3 Terminators SLVS-400 terminators are identical to SLVS-400 drivers in the LOW state, which is quite convenient for bidirectiona

23、l links and for preventing high-frequency stubs in receivers. 3 Parametrics SLVS-400 currents and impedances are specified in the context of odd-mode transmission-line impedances between 50 and 62 ohms (56 i2 f 10%). In the interest of standardization implementors should attempt to conform to this r

24、ange, but the whole point of SLVS is scalability and this applies to impedances as well as supply potentials. For lower or higher line impedances, the currents specified herein should be scaled linearly. 3.1 Power Supply SLVS-400 uses only one power supply: JEDEC Standard No. 8- 13 Page 3 ITH ITL i

25、TL2 3 Parametrics (contd) Minimum Voltage Maximum Voltage 8.0 mA 500 mV 6.4mA 320 mV 3.0 mA 200 mV 4.5mA 200 mV -3.0 mA -200 mV -4.5 mA -200 mV 3.2 Terminator parametrics ZTH ZTL Terminators have two critical operating points: 44 (Note 1) 68 i2 (Note 1) 44 i2 (Note 2) 68 i2 (Note 2) the static HIGH

26、operating point, where the terminator sets the steady-state current flowing in the line; this is the IT, operating point. the dynamic LOW operating region, where the terminator impedance (RDs(oNI) determines the line damping factor; this region is bounded by the ITL1 and ITL2 operating points. NOTE

27、1 between 320 mV and 500 mV Dynamic impedance (dV/di) must not exceed the specified limits for all operating points NOTE 2 Dynamic impedance (dV/di) must not exceed the specified limits for all operating points between -200 mV and 200 mV 3.3 Receiver parametrics Although performance requirements dic

28、tate that SLVS systems maintain balanced currents in both the driver and terminator devices, this does not necessarily mean strict differential (lB/2B) signaling. It is possible to save pins while maintaining DC balance using 4B/6B and 6B/8B coding as well, while using the mean potential of the code

29、 group as a receiver reference. The drawback to the non-differential coding schemes is that they have less than half of the signal amplitude at the receiver compared to differential signaling. SLVS receiver class I is sensitive enough to operate in this environment, while SLVS receiver class II requ

30、ires the full differential input signal swing. JEDEC Standard No. 8-13 Page 4 VREF 3.3 Receiver parametrics (contd) Minimum Maximum Notes 120 mV 280 mV 1 3.3.1 Class I receivers VIL(DC) VIH(DC) VIH(AC) VIX Class I receivers compare a single-ended input to a shared reference, VREF -300 mV VREF-90 mV

31、-300 mV VREF-50 mV VREF+50 mv 1150 mV VREF+90 mv 1150 mV 100 mV 300 mV 2 VIL(AC) Minimum Maximum Notes Dm+, Dm- 2 -300 mV Dm+ I Dm- - 160 mV NOTE 1 signal crosspoint voltage (VIX) will result in performance degradation. VREF generation is the responsibility of the system implementor. Deviations from

32、 the input VIX NOTE 2 VIX defines the range of input crossing points for which timing characterization remains valid. 100 mV 300 mV 1 3.3.2 Class II receivers Class II receivers compare two differential inputs, Dm+ and Dm-. VIL(DC) I Dm+, Dm- 2 -300 mV I Dm+ I Dm- - 100 mV I NOTE 1 VIX defines the r

33、ange of input crossing points for which timing characterization remains valid. JEDEC Standard No. 8- 13 Page 5 Minimum 3.4 Driver parametrics Maximum I Notes SLVS-400 defines two classes of drivers. Class A drivers are intended for point-to-point operation, so the load seen by the driver is nominall

34、y Zo. Class B drivers are intended for multidrop bus operation; the load seen by them is Z0/2. Since the endpoint devices in a multidrop environment effectively drive a single line (notably when they double as terminators when not driving the line) they can be Class A. In practice many implementatio

35、ns will allow for class selection. vox 3.4.1 Class A drivers 0.4 VOH 0.6 VOH 3 VOH I 320mVa-6.4rnA Iop I 3.0mA a200 mV IOLN I -3.0 mA -200 mV OH I 44 cl 68 cl ZOL I 44 cl 68 cl 12 NOTE 1 between 320 mV and 500 mV Dynamic impedance (dV/di) must not exceed the specified limits for all operating points

36、 NOTE 2 Dynamic impedance (dV/di) must not exceed the specified limits for all operating points between -200 mV and 200 mV NOTE 3 loads of between 50 and 62 ohms to ground. Output crosspoint voltage must remain within the specified limits relative to VOH for balanced JEDEC Standard No. 8-13 Page 6 3

37、.4 Driver parametrics (contd) 3.4.2 Class B drivers NOTE 1 between 320 mV and 500 mV Dynamic impedance (dV/di) must not exceed the specified limits for all operating points NOTE 2 between -200 mV and 200 mV Dynamic impedance (dV/di) must not exceed the specified limits for all operating points NOTE 3 loads of between 25 and 3 1 ohms to ground. Output crosspoint voltage must remain within the specified limits relative to V, for balanced