JEDEC JESD8-18A-2008 FBDIMM Specification High Speed Differential PTP Link at 1 5 V.pdf

1、JEDEC STANDARD FBDIMM Specification: High Speed Differential PTP Link at 1.5 V JESD8-18A (Revision of JESD8-18, SEPTEMBER 2006) MARCH 2008 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION SPECIAL DISCLAIMER: JEDEC has received information that certain patents or patent applications may be relevant to this s

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12、standard, and, as of the publication date of this standard, no statements regarding an assurance or refusal to license such patents or patent applications have been provided. http:/www.jedec.org/download/search/FBDIMM/Patents.xls JEDEC does not make any determination as to the validity or relevancy

13、of such patents or patent applications. Prospective users of the standard should act accordingly. JEDEC Standard No. 8-18A -i- FBDIMM HIGH SPEED DIFFERENTIAL PTP LINK AT 1.5 V Contents 1 Scope 1 1.1 Structure 1 1.2 Interconnect Definition 2 2 References 3 3 Terms and Definitions 3 3.1 D+ and D- 3 3.

14、2 Lane 3 3.3 Port 3 3.4 Link 4 3.5 Differential Signaling . 4 3.6 Unit Interval (UI) . 5 3.7 Transition Density in Transmitted Signals. 5 3.8 Jitter and BER 6 3.9 De-emphasis 6 3.10 Electrical Idle (EI) . 6 3.11 Reference Clock . 6 3.12 Front-End Transmitter and Receiver 7 3.13 List of Abbreviations

15、 and definitions . 8 4 Specification Details. 10 4.1 Clocking Specifications . 10 4.1.1 HCSL reference clocks 10 4.1.2 Reference Clock Frequency Tolerance . 10 4.1.3 Spread Spectrum Clocking (SSC) . 12 4.1.4 Reference Clock Jitter Spectrum . 12 4.1.5 Summary of Reference Clock Input Specifications .

16、 14 4.2 Common Specifications between Transmitter and Receiver 19 4.2.1 ESD Support 19 4.2.2 Short Circuit Requirements . 19 4.2.3 Hot Insertion and Removal . 19 4.2.4 Mode of Coupling 20 4.2.5 TX and RX Terminations . 20 4.2.6 TX and RX PLL Requirements 20 4.3 Differential Transmitter Output Specif

17、ications . 20 4.3.1 Transmitter Output Compliance Eye . 20 4.3.2 Transmitter Lane to Lane UI Specification 23 4.3.3 Summary of Transmitter Output Specifications 24 4.4 Differential Receiver Input Specifications . 27 4.4.1 Receiver Input Compliance Eye Specification . 27 4.4.2 Summary of Receiver Inp

18、ut Specifications 28 5 Compliance Methodology 33 5.1 Introduction . 33 5.2 Fundamentals of Jitter. 34 5.2.1 Jitter 34 5.2.2 Dual Dirac Model 36 5.3 High Speed Receiver 42 5.3.1 Calibration of jitter 42 5.3.2 Long Channel 42 JEDEC Standard No. 8-18A -ii- FBDIMM HIGH SPEED DIFFERENTIAL PTP LINK AT 1.5

19、 V Contents (contd) 5.3.3 Short Channel 44 5.3.4 Patterns 45 5.3.5 Measurement . 45 5.4 High Speed Transmitter 46 5.4.1 Clean Condition . 46 5.4.2 Realistic Condition . 46 5.4.3 Clean Patterns . 46 5.4.4 Realistic Patterns . 46 5.4.5 Measurement . 47 5.5 Low Speed Transmitter 48 5.6 Reference Clock

20、48 5.7 PLL Transfer Function. 49 5.8 Jitter Budget Explanation 50 5.9 “Clean” Reference Clock Input Specification 50 Annex A Revision History 54 Figures 1.1 TX to RX Connection 2 3.1 Sample Differential Signal. 5 3.2 De-emphasis 6 3.3 TX to RX Connection 7 4.1 Differential Reference CLK Waveform . 1

21、0 4.2 Reference Clock Absolute and Dynamic Ranges. 11 4.3 Phase Jitter Filter for Reference Clocks . 13 4.4 Single-ended Maximum and Minimum Levels and VcrossLevels . 17 4.5 Vcross-delta Definition . 17 4.6 Differential Edge Rate Definition 17 4.7 Rise and Fall Time Definition (for ERRefclk-Match on

22、ly) 18 4.8 VRB-diff and TStableDefinitions . 18 4.9 Definition of Transport Delay . 19 4.10 Transmitter Output Eye Specifications, with and without De-emphasis 21 4.11 Illustration of Timing Specification at TX 22 4.12 Illustration of De-emphasis at TX. 23 4.13 Receiver Input Eye Voltage and Timing

23、Specifications 27 4.14 RX Single-Pulse Min Width and Amplitude Mask, Pulse Shifted Early . 31 4.15 RX Single-Pulse Min Width and Amplitude Mask, Pulse Shifted Late 32 4.16 RX Maximum Adjacent Symbol Amplitude 32 4.17 RX Single-ended Electrical Idle Levels. 33 4.18 RX Common Mode Levels during Normal

24、 Operation (Small Swing Setting) 33 5.1 Phase Noise as f(t) and f(t) 34 5.2 Generation of a Cumulative Distribution Function from Time Domain Data. 36 5.3 Generation of a CDF from Time Domain Data (Left and Right Side) 36 5.4 Simple Gaussian Distribution using “BER” units and “Q” units. 37 5.5 Arbit

25、rary Distribution using “BER” units and “Q” units 39 5.6 CDF for Dual Dirac Model 41 5.7 PDF for Dual Dirac Model . 41 5.8 Sinusoidal Modulation Profile 43 5.9 Long Channel Receiver Compliance Test Setup 43 JEDEC Standard No. 8-18A -iii- FBDIMM HIGH SPEED DIFFERENTIAL PTP LINK AT 1.5 V Contents (con

26、td) 5.10 Short Channel Receiver Compliance Test Setup . 44 5.11 Transmit Jitter Extrapolation of DJdd, RJdd, and TJ . 48 5.12 Reference Clock Measurement Configurations 49 5.13 PLL Measurement Configurations 49 5.14 Clean Reference Clock Differential Amplitude 53 Tables 4.1 Summary of Reference Cloc

27、k Input Specifications. 14 4.2 PLL Specification for TX and RX . 20 4.3 Summary of Differential Transmitter Output Specifications 24 4.4 Summary of Differential Receiver Input Specifications. 28 5.1 Jitter Budget 50 5.2 Clean Reference Clock Input Specifications. 51 JEDEC Standard No. 8-18A -iv- FBD

28、IMM HIGH SPEED DIFFERENTIAL PTP LINK AT 1.5 V Introduction This specification is a JEDEC standard for the point-to-point link for the Fully Buffered DIMM. It is the result of a large amount of work from many people and is derived from prior internal specifications used at Intel Corporation with feed

29、back from external vendors and the JEDEC Fully-Buffered DIMM Link Signaling Task Group. JEDEC Standard No. 8-18A Page 1 FBDIMM HIGH SPEED DIFFERENTIAL PTP LINK AT 1.5 V (From JEDEC Board ballot JCB-06-01, JCB-06-60, JCB-06-61, and JCB-06-62, formulated under the cognizance of the JC-16 on Interface

30、technology.) 1 Scope This specification defines the high-speed differential point-to-point signaling link for FBDIMM, operating at the buffer supply voltage of 1.5V that is provided at the FBDIMM DIMM connector. This specification also applies to FBDIMM host chips which may operate with a different

31、supply voltage. The link consists of a transmitter and a receiver and the interconnect in between them. The transmitter sends serialized bits into a lane and the receiver accepts the electrical signals of the serialized bits and transforms them into a serialized bit-stream. The first generation FBDI

32、MM link is being specified to operate from 3.2 to 4.8 Gb/s. The specifications are defined for three distinct bit-rates of operation: 3.2 Gb/s, 4.0 Gb/s and 4.8 Gb/s. The link utilizes a derived clock approach and transmitter de-emphasis to compensate for channel loss characteristics. The link defin

33、ition has the flexibility to accommodate future silicon enhancement circuits such as forwarded clocking or advanced equalization techniques to meet future signaling targets. 1.1 Structure The specification is defined in four sections, covering the general signaling specifications for the silicon I/O

34、: Section 1covers the scope of the document, and defines important terms. Section 2 lists key reference documents. Section 3 defines important terms. Section 4 defines the interface requirements and is divided into four subsections: Section 4.1 defines the clocking requirements. Section 4.2 defines

35、common requirements for both transmitter and receiver. Section 4.3 defines requirements that are unique to the transmitter. Section 4.4 defines requirements that are unique to the receiver. Section 5 defines measurement and compliance testing procedures. The interconnect between transmitter and rece

36、iver is not directly specified but implied by the difference between receiver and transmitter specifications. The interconnect needs to have a smooth enough characteristic to be operational at the frequencies which it is intended to support. JEDEC Standard No. 8-18A Page 2 1.2 Interconnect Definitio

37、n The overall budget for voltage and timing margins are divided into transmitter (TX), interconnect, and receiver (RX) specifications. The link signaling specifications defines the TX and RX requirements at the package pins. In the context of this specification, the interconnect consists of everythi

38、ng between the pins at a transmitter package and the pins of a receiver package. The interconnect components in FBDIMM are socket(s) (if used), PCB (printed circuit board(s) and connector(s). Interconnect voltage and timing budgets are derived from the output specifications of the TX and the input s

39、pecifications for the RX. Note that the TX and RX termination (specified in Table 4.3 and Table 4.4) and the test load are 50 (specified in Section 5). Figure 1.1 depicts the compliance measurement points to capture each portion of the budget. The transmitter and receiver parameters are defined into

40、 test loads. This methodology ensures that the channel interactions are not included in the TX and RX measurement. Figure 1.1 TX to RX Connection The transmitter, receiver, and reference clock specifications presented in Section 4 have been derived based on analysis of two specific interconnects: a

41、host-to-first-DIMM interconnect and a DIMM-to-DIMM interconnect. The interconnect descriptions provided below are not intended to be used as a design specification. System designers must perform thorough analysis of any proposed FBD interconnect. The interconnect model used to analyze the host-to-fi

42、rst-DIMM configuration has the following components: MB trace (host to connector): 3.0 to 12.0 inches Optional riser card trace: connector to connector: 2.0 to 5.0 inches DIMM trace (DIMM connector to AMB): 0.33 to 2.0 inches The interconnect model used to analyze the DIMM-to-DIMM configuration has

43、the following components: DIMM trace (AMB to DIMM connector): 0.33 to 2.0 inches Motherboard trace: connector to connector: 0.5 to 2.0 inches DIMM trace (DIMM connector to AMB): 0.33 to 2.0 inches JEDEC Standard No. 8-18A Page 3 1.2 Interconnect Definition The analysis was performed assuming FR4 PCB

44、 dielectric for both motherboard and DIMM; the differential impedance (ZDIFF) was 85 15% for motherboard and DIMM stripline traces and was 85 20% for DIMM microstrip traces. Note that using the above description as a system design recipe is not enough to guarantee a working channel. The range of ach

45、ievable lengths may be narrower or wider than the above, depending on materials, stackups, trace geometries, and other design choices. 2 References The following documents contain provisions that, through references in this text, constitute provisions of this specification. For dated references, sub

46、sequent amendments to, or revisions of, any of these publications do not apply. However, parties to agreements based on this specification are encouraged to investigate the possibility of applying the most recent editions of the referenced documents below. For undated references, the latest edition

47、of the document referred to applies. JEDEC JC-40, FBDIMM Architecture and Protocol Draft Specification INTEL, FBD240 Connector Draft Specification JEDEC JC-40, Advanced Memory Buffer Design Draft Speciation JEDEC JC-45, FB4300/5300/6400 DDR Fully Buffered DIMM Design Specification JEDEC MO-256B, Ful

48、ly Buffered Dual Inline Memory Module Family. (Module Outline) JEDEC SO-003, FBDIMM Socket Outline JEDEC JESD22A114, Electrostatic Discharge (ESD) Sensitivity Testing (HBM) 3 Terms and Definitions 3.1 D+ and D- The D+ and D- terms used in this document are used to indicate the two conductors or sign

49、als of a differential signaling pair. 3.2 Lane One differential pair in one direction, consisting of a D+ and a D- conductor. 3.3 Port In physical terms, a group of transmitters and receivers physically located on the same chip that define a Link. JEDEC Standard No. 8-18A Page 4 3 Terms and Definitions (contd) 3.4 Link A dual-simplex communications path between two components. The collection of two Ports and their interconnecting Lanes. 3.5 Differential Signaling A Differential Signal is defined by taking the voltage difference between two conductors. In t