JEDEC JESD8-23-2009 Unified Wide Power Supply Voltage Range CMOS DC Interface Standard for Non-Terminated Digital Integrated Circuits.pdf

1、JEDEC STANDARD Unified Wide Power Supply Voltage Range CMOS DC Interface Standard for Non-Terminated Digital Integrated Circuits JESD8-23 OCTOBER 2009 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved thro

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10、7559 JEDEC Standard No. 8-23 Page 1 UNIFIED WIDE POWER SUPPLY VOLTAGE RANGE CMOS DC INTERFACE STANDARD FOR NON-TERMINATED DIGITAL INTEGRATED CIRCUITS (From JEDEC Board Ballot JCB-09-50, formulated under the cognizance of the JC-16 Committee on Interface Technology. ) 1 Scope This standard defines DC

11、 interface parameters and test conditions for a family of non-terminated CMOS digital circuits intended for use over a wide power supply voltage range. The standard bridges a number of existing JEDEC standards in the JESD8-x family to facilitate applications that operate over an ultra-wide power sup

12、ply voltage range in order to achieve lower power dissipation or higher performance. Three voltage range categories (1, 2 and 3) are defined to support a variety of application requirements. A design claiming compliance with the standard must specifically identify the category or categories supporte

13、d. This standard specifically does not include interfaces to DDR2 (JESD79-2) or DDR3 (JESD79-3) devices. 2 Standard specification All voltages are referenced to ground except where noted. 2.1 Absolute maximum continuous ratings Parameter Category Range NOTE 1 -0.5 V to 4.6 V 1 2 -0.5 V to 3.6 V 1 Su

14、pply Voltage, VDD3 -0.5 V to 2.5 V 1 dc Input Voltage, VIN (except I/O pins) -0.5 V to VDD +0.5 V 1,2,3 dc Output Voltage, VOUT (including I/O pins) -0.5 V to VDD +0.5 V 2,3 dc Input Diode Current, II K (VIN VDD) +/- 20mA dc Output Diode Current, IOK (VOUT VDD) +/- 20mA NOTE 1 Absolute maximum conti

15、nuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum conditions is not implied. NOTE 2 Not to exceed maximum VDD.NOTE 3 Range limited to “-0

16、.4 V to VDD +0.4V“ when VDD is less than 1.1V. JEDEC Standard No. 8-23 Page 2 2 Standard specifications (contd) 2.2 Recommended operating conditions Symbol Parameter Category (NOTE 1) Operating Range (NOTE 2)1 1.65 V to 3.6 V 2 1.4 V to 2.7 V VDDPower Supply Voltage 3 0.7 V to 1.95 V TAOperating Tem

17、perature - (NOTE 3) NOTE 1 Categorized by manufacturer for each application. An application may support one or more categories. NOTE 2 Specified according to recommended operating conditions for each device. NOTE 3 Specified by manufacture to be commercial, industrial, and/or military grade. 2.3 DC

18、electrical characteristics Symbol Parameter Test Condition MIN MAX Unit VIHInput High Voltage 0.7VDDVDD+0.3 V VILInput Low Voltage -0.3 0.3VDDV VOHOutput High Voltage IOH= -100uA 0.85VDD- V VOLOutput Low Voltage IOL= 100uA - 0.15VDDV NOTE 1 For VIHand VIL, VDDrefers to the receiving device. For VOHa

19、nd VOL, VDDrefers to the sending device. 2.4 DC electrical characteristics for Schmitt trigger operation Symbol Parameter Test Condition MIN MAX UnitVt+ (Vp) Positive Going Threshold Voltage VOUTVOH(min) 0.35VDD0.75VDDV Vt- (Vn) Negative Going Threshold Voltage VOUTVOL(max) 0.25VDD0.65VDDV VH (Vt) H

20、ysteresis Voltage Vt+ - Vt- 0.1VDD0.5VDDV VOHOutput High Voltage IOH= -100uA 0.85VDD- V VOLOutput Low Voltage IOL= 100uA - 0.15VDDV NOTE 1 For Vt+ (Vp) and Vt- (Vn), VDDrefers to the receiving device. For VOHand VOL, VDDrefers to the sending device. JEDEC Standard No. 8-23 Page 3 3 Test conditions 3

21、.1 Positive Going Threshold Voltage: Vt+ (Vp) As the input signal is raised from a ground level in the measurement circuit shown in Figure 1, the input voltage value of which output logic changed is determined as Vt+ (Vp). 3.2 Negative Going Threshold Voltage: Vt- (Vn) As the input signal is dropped

22、 from a power supply voltage level in the measurement circuit shown in Figure 1, the input voltage value of which output logic changed is determined as Vt- (Vn). Figure 1 DC characteristic measurement circuit of Schmitt trigger input JEDEC Standard No. 8-23 Page 4 Standard Improvement Form JEDEC JES

23、D8-23 The purpose of this form is to provide the Technical Committees of JEDEC with input from the industry regarding usage of the subject standard. Individuals or companies are invited to submit comments to JEDEC. All comments will be collected and dispersed to the appropriate committee(s). If you

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