JEDEC JESD8-24-2011 POD12 1 2 V PSEUDO OPEN DRAIN INTERFACE.pdf

1、JEDEC SOLID STATE TECHNOLOGY ASSOCIATIONJESD824AUGUST 2011JEDECSTANDARDPOD12 1.2 V PSEUDO OPENDRAIN INTERFACE NOTICEJEDEC standards and publications contain material that has been prepared, reviewed, andapproved through the JEDEC Board of Directors level and subsequently reviewed and approvedby the

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6、the standard are met.Inquiries, comments, and suggestions relative to the content of this JEDEC standard orpublication should be addressed to JEDEC at the address below, or call (703) 9077559 orwww.jedec.orgPublished byJEDEC Solid State Technology Association 20093103 North 10th StreetSuite 240 Sout

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8、ublications online athttp:/www.jedec.org/Catalog/catalog.cfmPrinted in the U.S.A.All rights reservedPLEASE!DONT VIOLATETHELAW!This document is copyrighted by the JEDEC Solid State Technology Associationand may not be reproduced without permission.Organizations may obtain permission to reproduce a li

9、mited number of copies through entering into a license agreement. For information, contact:JEDEC Solid State Technology Association3103 North 10th Street, Suite 240SArlington, Virginia 22201or call (703) 9077559JEDEC Standard No. 8-24Page 1POD12 - 1.2 V PSEUDO OPEN DRAIN INTERFACE(From JEDEC Board B

10、allot JCB-11-46, formulated under the cognizance of the JC-16 Committee on Inter-face Technology.)1 ScopeThis document defines the 1.2 V Pseudo Open Drain Interface family of interface standards, POD12, which are generally expected to be implemented with differential amp-based input buffers that, wh

11、en in single-ended mode, employ an externally supplied (or internal supplied) reference voltage controlled trip-point. Although this standard is named for the nominal value of VDDQ to be used, it is the input trip-point value that provides for inter operability of POD12 compliant devices. Physics di

12、ctates variations in output driver characteristics and termination values in different interconnect network topologies. Drivers and terminators appropriate in a point-to-point interconnect scheme are not necessarily suitable in a multi-drop bus application. Multiple Classes of POD12 are expected to

13、reside within the family of POD12 interfaces in order to accommodate various device and market applications. The various classes standardized within the context of POD12 are documented in the annex of this document (e.g., POD12/Class A, POD12/Class B, POD12/Class C, etc.)In all cases, drivers and te

14、rminators are expected to produce a roughly symmetric swing about the input trip-point of POD12 receivers. Unlike the signals on other interfaces, such as HSTL, that are designed to produce signals that swing symmetrically about VDDQ/2, the signals on a POD12 interconnect line are not generally expe

15、cted to pull to VSS. POD12 input buffers are generally expected to be supported by pull-up-only parallel input termination. POD12 output drivers are therefore expected to demonstrate an asymmetric output drive impedance. In point-to-point applications, for example, if the output drivers were expecte

16、d to demonstrate a nominal 60 ohm pull-up drive impedance then the pull-down drivers would be expected to produce a 40 ohm pull-down drive impedance.The core of this standard defines the dc and ac single-ended and differential operating conditions for POD12 input buffers as well as the terms and def

17、initions necessary to describe the characteristics and behavior of output drivers. Clause 2 documents the subset of values common to all Classes of POD12 and documents specification items left to definition within a specific Class. The values specific to each particular class of POD12 are found in t

18、he annex. (Note it does not follow that all specification values defined in a given Class are necessarily different from the matching parameter in other Class within POD12. Multiple Classes may reuse a given specification value if appropriate to the Class requirements.)Inasmuch as additional classes

19、 may be added to this standard at the will of the authorizing committee and the JEDEC Board of Directors, the reader is advised to check the JEDEC website (http:/www.jedec.org) for the latest release of the standard.JEDEC Standard No. 8-24Page 22 Core POD12 interface specificationsTable 2-1 DC opera

20、ting conditionsTable 2-2 AC operating conditions.Parameter SymbolPOD12Unit NoteMin Typ MaxDevice Supply Voltage VDD n/a n/a n/a V 1Output Supply Voltage VDDQ CDV 1.2 CDV V 2Reference Voltage VREF CDV CDV CDV V 3DC Input Logic HIGH Voltage VIH (DC) CDV CDV VDC Input Logic LOW Voltage VIL (DC) CDV CDV

21、 VInput Leakage CurrentAny Input 0 V = VIN= VDDQ(All other pins not under test = 0 V) Il A 4Output Leakage Current ( DQs are disabled; 0V = Vout = VDDQ)Ioz A 4Output Logic LOW Voltage VOL (DC) 0.5 VNotes: 1) The POD12 interface may be implemented on any device without regard to VDD. Although VDD can

22、 generally be expected to greater than or equal to VDDQ, compliant devices may support VDD values lower than VDDQ.2) POD12 compliant devices are expected to tolerate PCB designs with separate VDD and VDDQ power regulators.3) The source of Reference Voltage and control of Reference Voltage, and assoc

23、iation of Reference Voltage with specific I/O pins may be determined control mechanisms specified by the device vendor.4) These parameters are expected to be standardized by product type and are therefore left blank intentionally here.Notice: CDV means Class Dependent Value. See specific Class table

24、s for further details.Parameter SymbolPOD12Unit NoteMin Typ MaxAC Input Logic HIGH Voltage VIH (AC) CDV VAC Input Logic Low Voltage VIL (AC) CDV VNotice: CDV means Class Dependent Value. See specific Class tables for further details.JEDEC Standard No. 8-24Page 32 Core POD12 interface specifications

25、(contd)Figure 2-1 Voltage waveformVIL (AC)VIL (DC)VREF DC NoiseVREF DC NoiseVREF + DC NoiseVREF + AC NoiseVIH (DC)VIH (AC)VOHVIN (AC) Provides marginbetween VOL (MAX) andVIL (AC)VOL (MAX)System Noise Margin (Power/Ground, Crosstalk, Signal Integrity Attenuation)OutputInputJEDEC Standard No. 8-24Page

26、 42 Core POD12 interface specifications (contd)Table 2-3 Differential input operating conditionsParameter SymbolPOD12Unit NoteMin MaxDif Input Mid-Point Voltage; Pin and Pin# VMP (DC) CDV CDV V 1Dif Input Differential Voltage; Pin and Pin# VID (DC) CDV V 1, 3Dif Input Differential Voltage; Pin and P

27、in# VID (AC) CDV V 1, 2, 3Single-ended Input Voltage; Pin and Pin# VIN CDV CDV 1Single-ended Input Voltage Slew Rate; Pin and Pin# VINS CDV V/ns 4Dif Input Crossing Point Voltage; Pin and Pin# VIX (AC) CDV CDV V 2Allowed time before ringback to VID (AC) tDVACps 2, 9Notes:1) “Pin” and “Pin#” represen

28、t the true and compliment pins of a differential input pair.2) For AC operations, all DC requirements must be satisfied as well.3) VID is the magnitude of the difference between the input level in Pin and the input level on Pin#.4) The slew rate is measured between VREF crossing and VIX (AC).5) The

29、Pin and Pin# input reference level (for timing referenced to Pin and Pin#) is the point at which Pin and Pin# cross. 6) Figure 2-3: illustrates the exact relationship between (Pin-Pin#) and VID(AC), VID(DC) and tDVAC7) Ringback voltage on Pin or Pin# below VID(DC) is not allowed.8) tDVACis not measu

30、red in and of itself as a compliance specification, but is relied upon in measurement of Pin operating conditions and Pin related parameters.9) This parameter is expected to be standardized by product type and is therefore left blank intentionally here.Notice: CDV means Class Dependent Value. See sp

31、ecific Class tables for further details.JEDEC Standard No. 8-24Page 52 Core POD12 interface specifications (contd)Figure 2-2 Pin waveformVIX(AC)Pin#PinMaximum Input LevelMinimum Input LevelVID (AC)VID (DC)VMP (DC)JEDEC Standard No. 8-24Page 62 Core POD12 interface specifications (contd)Figure 2-3 De

32、finition of differential ac-swing and “time above ac-level” tDVACThe Driver and Termination impedances should be characterized under the following test conditions:1) Set VDDQ to Nominal.2) Power the compliant device and calibrate the output drivers and termination to eliminate process variation at 2

33、5 C.3) Reduce temperature to the device low operating temperature limit plus 10 C and recalibrate.4) Reduce temperature to low operating temperature limit and take the fast corner measurement.5) Raise temperature to the device high operating temperature limit minus 10 C and recalibrate.6) Raise temp

34、erature to high operating temperature limit and take the slow corner measurement.7) Reiterate 2 to 6 with VDDQ at Max limit.8) Reiterate 2 to 6 with VDDQ at Min limit.0VID (AC) MINtDVACtDVAChalf cycletimeDifferentialInputVoltage(i.e.V(Pin) V(Pin#)VID (DC) MIN(VID (DC) MIN)(VID (AC) MIN)JEDEC Standar

35、d No. 8-24Page 73 Drive strength and termination issuesInasmuch as the POD12 interface can be useful for interconnecting many sorts of high speed devices, operating in significantly divergent price/performance and power domains, compliant devices are not required to offer on-die input termination. N

36、evertheless on-die input termination is expected to be the norm for POD12 compliant devices.In order to achieve sufficient precision in drive strength and termination impedance over process, temperature and voltage variations, compliant devices are generally expected to implement some sort of impeda

37、nce control scheme on output drivers and on-die input terminators, if present. Best practices dictate drivers and terminators maintain their target impedance (+/- 20% or better) over a voltage of VDDQ * 0.20 to VDDQ * 0.80. Specific device types with particular interface speed requirements are expec

38、ted to establish specific control schemes and precision requirements within the POD12 framework that are appropriate to their target applications.JEDEC Standard No. 8-24Page 8Annex A (normative) POD12/Class APOD12/Class A is intended for point-to-point interconnect applications.Table A-1 DC operatin

39、g conditionsTable A-2 AC operating conditionsParameter SymbolPOD12Unit NoteMin Typ MaxDevice Supply Voltage VDD n/a n/a n/a V 1Output Supply Voltage VDDQ 1.16 1.2 1.24 V 2Reference Voltage VREF 0.69 * VDDQ0.70 * VDDQ0.71 * VDDQ V 3, 4DC Input Logic HIGH Voltage VIH (DC) VREF + 0.08 VDDQ + 0.15 VDC I

40、nput Logic LOW Voltage VIL (DC) -0.15 VREF - 0.08 VInput Leakage CurrentAny Input 0V = VIN= VDDQ(All other pins not under test = 0V) Il A 5Output Leakage Current (DQs are disabled; 0V = Vout = VDDQ)Ioz A 5Output Logic LOW Voltage VOL (DC) 0.5 VNotes: 1) The POD12 interface may be implemented on any

41、device without regard to VDD. Although VDD can generally be expected to greater than or equal to VDDQ, compliant devices may support VDD values lower than VDDQ.2) POD12 compliant devices are expected to tolerate PCB designs with separate VDD and VDDQ power regulators.3) The design of POD12 anticipat

42、es boards that use POD12 compliant devices will control AC noise to 50 mV pk-pk or less.4) The source of Reference Voltage and control of Reference Voltage, and association of Reference Voltage with specific I/O pins may be determined control mechanisms specified by the device vendor.5) These parame

43、ters are expected to be standardized by product type and are therefore left blank intentionally here.Parameter SymbolPOD12Unit NoteMin Typ MaxAC Input Logic HIGH Voltage VIH (AC) VREF + 0.15 VAC Input Logic Low Voltage VIL (AC) VREF - 0.15 VJEDEC Standard No. 8-24Page 9Annex A (normative) POD12/Clas

44、s A (contd)Table A-3 Differential input operating conditionsParameter SymbolPOD12Unit NoteMin MaxDif Input Mid-Point Voltage; Pin and Pin# VMP (DC) VREF - 0.08 VREF + 0.08 V 1Dif Input Differential Voltage; Pin and Pin# VID (DC) 0.16 V 1, 3Dif Input Differential Voltage; Pin and Pin# VID (AC) 0.30 V

45、 1, 2, 3Single-ended Input Voltage; Pin and Pin# VIN 0.27 VDDQ + 0.15 1Single-ended Input Voltage Slew Rate; Pin and Pin# VINS 3 V/ns 4Dif Input Crossing Point Voltage; Pin and Pin# VIX (AC) VREF - 0.08 VREF + 0.08 V 2Allowed time before ringback to VID (AC) tDVACps 2, 9Notes:1) “Pin” and “Pin#” rep

46、resent the true and compliment pins of a differential input pair.2) For AC operations, all DC requirements must be satisfied as well.3) VID is the magnitude of the difference between the input level in Pin and the input level on Pin#.4) The slew rate is measured between VREF crossing and VIX (AC).5)

47、 The Pin and Pin# input reference level (for timing referenced to Pin and Pin#) is the point at which Pin and Pin# cross. 6) Figure 2-3: illustrates the exact relationship between (Pin-Pin#) and VID(AC), VID(DC) and tDVAC7) Ringback voltage on Pin or Pin# below VID(DC) is not allowed.8) tDVACis not

48、measured in and of itself as a compliance specification, but is relied upon in measurement of Pin operating conditions and Pin related parameters.9) This parameter is expected to be standardized by product type and is therefore left blank intentionally here.JEDEC Standard No. 8-24Page 10Rev. 9/02 St

49、andard Improvement Form JEDEC The purpose of this form is to provide the Technical Committees of JEDEC with input from the industry regarding usage of the subject standard. Individuals or companies are invited to submit comments to JEDEC. All comments will be collected and dispersed to the appropriate committee(s). If you can provide input, please complete this form and return to: JEDEC Attn: Publications Department 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 Fax: 703.907.7583 1. I recommend changes to the following: Requi