JEDEC JESD80-1999 Standard for Description of 2 5 V CMOS Logic Devices《2 5 V CMOS逻辑设备的描述标准》.pdf

1、JEDECSTANDARDStandard for Description of 2.5 VCMOS Logic DevicesJESD80NOVEMBER 1999ELECTRONIC INDUSTRIES ALLIANCEJEDEC Solid State Technology AssociationNOTICEEIA/JEDEC standards and publications contain material that has been prepared, reviewed, andapproved through the JEDEC Board of Directors leve

2、l and subsequently reviewed and approvedby the EIA General Counsel.EIA/JEDEC standards and publications are designed to serve the public interest througheliminating misunderstandings between manufacturers and purchasers, facilitatinginterchangeability and improvement of products, and assisting the p

3、urchaser in selecting andobtaining with minimum delay the proper product for use by those other than JEDEC members,whether the standard is to be used either domestically or internationally.EIA/JEDEC standards and publications are adopted without regard to whether or not theiradoption may involve pat

4、ents or articles, materials, or processes. By such action JEDEC does notassume any liability to any patent owner, nor does it assume any obligation whatever to partiesadopting the EIA/JEDEC standards or publications.The information included in EIA/JEDEC standards and publications represents a sound

5、approachto product specification and application, principally from the solid state device manufacturerviewpoint. Within the JEDEC organization there are procedures whereby an EIA/JEDECstandard or publication may be further processed and ultimately become an ANSI/EIA standard.No claims to be in confo

6、rmance with this standard may be made unless all requirements stated inthe standard are met.Inquiries, comments, and suggestions relative to the content of this EIA/JEDEC standard orpublication should be addressed to JEDEC Solid State Technology Association, 2500 WilsonBoulevard, Arlington, VA 22201

7、-3834, (703)907-7560/7559 or www.jedec.orgPublished by ELECTRONIC INDUSTRIES ALLIANCE 19992500 Wilson BoulevardArlington, VA 22201-3834This document may be downloaded free of charge, however EIA retains thecopyright on this material. By downloading this file the individual agrees not tocharge or res

8、ell the resulting material.PRICE: Please refer to the currentCatalog of JEDEC Engineering Standards and Publications or call Global EngineeringDocuments, USA and Canada (1-800-854-7179), International (303-397-7956)Printed in the U.S.A.All rights reservedPLEASE!DON”T VIOLATETHELAW!This document is c

9、opyrighted by the Electronic Industries Alliance and may not bereproduced without permission.Organizations may obtain permission to reproduce a limited number of copiesthrough entering into a license agreement. For information, contact:JEDEC Solid State Technology Association2500 Wilson BoulevardArl

10、ington, Virginia 22201-3834or call (703) 907-7559JEDEC Standard No. 80Page 1STANDARD FOR DESCRIPTION OF 2.5 V CMOS LOGIC DEVICES(Formerly JEDEC Board Ballot JCB-99-50, formulated under the cognizance of the JC-40 Committee on Digital Logic.)1 PurposeTo provide a standard for 2.5-V nominal supply-vol

11、tage CMOS logic devices, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.2 Scope This standard defines dc interface parameters and test loading for a CMOS digital logic family based on 2.5-V (nominal) power supply levels and 2.5-V inpu

12、t tolerance.3 Terms and definitions For the purpose of this document, the following term and definition apply.3.1 PrefixesPrefixes “54“ or “74“ immediately preceding family name indicate the operating temperature range. For example, 54XXX refers to the Military (MIL) version of devices which are spe

13、cified over the temperature range of 55 C to 125 C. 74XXX refers to the Commercial (COML) version of devices which are specified over 40 C to 85 C.4 Standard specification4.1 Absolute maximum ratingsTable 1 Absolute maximum ratings over operating free-air temperature range (see Note 1)Supply voltage

14、 range, VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to 3.6 VInput voltage range, VI: Except I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to VDD+ 0.5 VI/O ports (see Note 2). . . . . . . . . .

15、. . . . . . . . . . . . . . . . . . . . . 0.5 V to VDD + 0.5 VOutput voltage range, VO(see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to VDD+ 0.5 VVoltage range applied to any output in the high-impedance stateor power-off state, VO. . . . . . . . . . . .

16、. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VDD + 0.5 VStorage temperature range, TSTG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 C to 150 CNOTES1 Stresses beyond those listed under “absolute maximum ratings

17、“ may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions“ is not implied. Exposure to absolute-maximum-rated conditions for extended periods may af

18、fect device reliability.2 This value is limited to 3.6 V maximum.JEDEC Standard No. 80Page 24.2 Recommended operating conditionsNOTES1 Unused control inputs must be held high or low to prevent them from floating.2 Normal range operating conditions per JESD8-53 Wide range operating conditions per JES

19、D8-54 As measured between 0.7 V and 1.7 VTable 2 Recommended operating conditions (see Note 1)Min Max UnitVDDSupply voltageOperating 1.8 2.7VData retention only 1.2VIHHigh-level input voltageVDD= 2.3 V to 2.7 V (see Note 2)1.7VDD+ 0.3V1.8 V VDD 2.3 V (see Note 3) 0.7 VDDVDD+ 0.3VILLow-level input vo

20、ltageVDD= 2.3 V to 2.7 V (see Note 2) 0.3 0.7V1.8 V VDD 2.3 V (see Note 3)0.30.2 VDDVIInput voltage 0VDDVVOOutput voltage 0 VDDVt / v Input transition rise or fall rate (see Note 4) 0 10 ns/VTAOperating free-airtemperature54 series 55 125C74 series 40 85JEDEC Standard No. 80Page 34.3 DC specificatio

21、nsNOTES1 The bus hold circuit can sink at least the minimum low sustaining current at VILmax. IBHLshould be measured after lowering VINto GND and then raising it to VILmax.2 The bus hold circuit can source at least the minimum high sustaining current at VIHmin. IBHHshould be measured after raising V

22、INto VDDand then lowering it to VIHmin.3 An external driver must source at least IBHLOto switch this node from low to high.4 An external driver must sink at least IBHHOto switch this node from high to low.5 For I/O ports, the parameter IOZincludes the input leakage current.Table 3 Electrical charact

23、eristics over recommended operating free-air temperature rangeParameter Test Conditions VDDMin Max UnitVOHIOH= 100 A1.8 V 1.6VIOH= 1 mA, VIH= 1.7 V 2.3 V 2IOH= 8 mA, VIH= 1.7 V2.3 V 1.8VOLIOL= 100 A1.8 V 0.2VIOL= 1 mA, VIL= 0.7 V 2.3 V 0.4IOL= 8 mA, VIL= 0.7 V2.3 V 0.6IIVI= VDDor GND 2.7 V 10 AIBHL(

24、see Note 1)VI= 0.7 V 2.3 V 45 AIBHH(see Note 2)VI= 1.7 V2.3 V 45 AIBHLO(see Note 3)VI= 0 to VDD2.7 V 500 AIBHHO(see Note 4)VI= 0 to VDD2.7 V 500 AIOZ(see Note 5)VO= VDDor GND 2.7 V 10 AIDDVI= VDDor GND, IO= 0 2.7 V 20 A Specification only for components with optional bus hold.JEDEC Standard No. 80Pa

25、ge 45 Test circuit and switching waveformsFigure 1 Parameter Measurement Information (VDD= 1.8 V to 2.7 V)NOTES1 CL includes probe and jig capacitance.2 Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an o

26、utput with internal conditions such that the output is high except when disabled by the output control.3 All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO= 50 , tr 2 ns, tf 2 ns, measured from 10% to 90%, unless otherwise specified.4 The outputs are mea

27、sured one at a time with one transition per measurement.6 Reference to other applicable JEDEC standards and publicationsJESD8-5: 2.5 V 0.2 V (Normal Range), and 1.8 V to 2.7 V (Wide Range) Power Supply Voltage and Interface Standard for Nonterminated Digital Integrated Circuits.2 VDDOpenGNDRL= 500CL

28、 = 30 pF(see Note 1)From OutputUnder TestLOAD CIRCUITTESTtpdtPLZ/tPZLtPHZ/tPZHS1Open2 VDDGNDVDD/2VDD/2VDD/2VDD/2 VDD/2VDD/2VDD/2VDD/2 VDD/2VDD/2 VDD/2VDD/2VDD/2VOH 0.15 VVDDVDDVDDVOHVDDVDDVDDVOHVOLVOL0 V0 V0 V0 V0 V0 VVOL+ 0.15 VTimingInputDataInputInputOutputInputOutputControl(low-levelenabling)OutputWaveform 1S1 at 2 VDD(see Note 2)OutputWaveform 2S1 at GND(see Note 2)tsuthtPHLtPLHtPLZtPHZtPZLtPZHtwVOLTAGE WAVEFORMS PULSE DURATIONVOLTAGE WAVEFORMS ENABLE AND DISABLE TIMESVOLTAGE WAVEFORMS PROPAGATION DELAY TIMESVOLTAGE WAVEFORMS SETUP AND HOLD TIMES