JEDEC JESD82-13A-2005 Definition of the SSTVN16859 2 5-2 6 V 13-Bit to 26-Bit SSTL 2 Registered Buffer for PC1600 PC2100 PC2700 and PC3200 DDR DIMM Applications《SSTVN16859 2 5-2 6V.pdf

1、JEDEC SOLID STATE TECHNOLOGY ASSOCIATIONJESD82-13AMAY 2005JEDECSTANDARDDefinition of the SSTVN16859 2.5-2.6 V 13-Bit to 26-Bit SSTL_2 Registered Buffer for PC1600, PC2100, PC2700and PC3200 DDR DIMM Applications(Revision of JESD82-13)NOTICE JEDEC standards and publications contain material that has b

2、een prepared, reviewed, and approvedthrough the JEDEC Board of Directors level and subsequently reviewed and approved by the JEDECLegal Counsel. JEDEC standards and publications are designed to serve the public interest through eliminatingmisunderstandings between manufacturers and purchasers, facil

3、itating interchangeability andimprovement of products, and assisting the purchaser in selecting and obtaining with minimum delaythe proper product for use by those other than JEDEC members, whether the standard is to be usedeither domestically or internationally. JEDEC standards and publications are

4、 adopted without regard to whether or not their adoption mayinvolve patents or articles, materials, or processes. By such action JEDEC does not assume anyliability to any patent owner, nor does it assume any obligation whatever to parties adopting theJEDEC standards or publications. The information

5、included in JEDEC standards and publications represents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. No claims to be in conformance with this standard may be made unless all requirements stated in thestandard are met. Inqu

6、iries, comments, and suggestions relative to the content of this JEDEC standard or publicationshould be addressed to JEDEC Solid State Technology Association, 2500 Wilson Boulevard,Arlington, VA 22201-3834, (703)907-7559 or www.jedec.org. Published by JEDEC Solid State Technology Association 2005 25

7、00 Wilson Boulevard Arlington, VA 22201-3834 This document may be downloaded free of charge, however JEDEC retains the copyright on this material. By downloading this file the individual agrees not to charge for or resell the resulting material. Price: Please refer to the current Catalog of JEDEC En

8、gineering Standards and Publications at www.jedec.org Printed in the U.S.A. All rights reserved PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by the JEDEC Solid State Technology Association and may not be reproduced without permission. Organizations may obtain permission to reproduce a

9、limited number of copies through entering into a license agreement. For information, contact: JEDEC Solid State Technology Association 2500 Wilson Boulevard Arlington, Virginia 22201-3834 or call (703) 907-7559 JEDEC Standard No. 82-13APage 1STANDARD FOR DEFINITION OF THE SSTVN16859 2.52.6-V 13-BIT

10、TO 26-BIT SSTL_2REGISTERED BUFFER FOR DDR DIMM APPLICATIONS(From JEDEC Board Ballot JCB-04-74 and JCB-05-11, formulated under the cognizance of the JC-40 Committee on Digital Logic.)1 ScopeThis standard defines standard specifications of dc interface parameters, switching parameters, and test loadin

11、g for definition of the SSTVN16859 13-bit to 26-bit SSTL_2 registered buffer for PC1600, PC2100, PC2700 and PC3200 DDR DIMM applications. The SSTVN16859 is a speed upgrade of the SSTV16859 (JESD82-4) for use in PC3200 DDR DIMMs. It is fully backward compatible with SSTV16859 for all speed grades.The

12、 purpose is to provide a standard for the SSTVN16859 (see Note) logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.NOTE The designation SSTVN16859 refers to the part designation of a series of commercial logic parts common i

13、n the industry. This number is normally preceeded by a series of manufacturer specific characters to make up a complete part designation.2 Device standard2.1 DescriptionThis 13-bit to 26-bit registered buffer is designed for 2.3-V to 2.7-V VDD(PC1600, PC2100, PC2700) and 2.5-V to 2.7-V VDD(PC3200) o

14、peration.All inputs are compatible with the JEDEC standard for SSTL_2, except the LVCMOS reset (RESET) input. All outputs are SSTL_2, Class II compatible.The SSTVN16859 operates from a differential clock (CK and CK). Data are registered at the crossing of CK going high, and CK going low.The device s

15、upports low-power standby operation. When RESET is low, the differential input receivers are disabled, and undriven (floating) data, clock and reference voltage (VREF) inputs are allowed. In addition, when RESET is low all registers are reset, and all outputs are forced low. The LVCMOS RESET input m

16、ust always be held at a valid logic high or low level.To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power up.In the DDR DIMM application, RESET is specified to be completely asynchronous with respect to CK and CK. Ther

17、efore, no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared and the outputs will be driven low quickly, relative to the time to disable the differential input receivers, thus ensuring no glitches on the output. However, when coming out of reset,

18、 the register will become active quickly, relative to the time to enable the differential input receivers. As long as the data inputs are low, and the clock is stable during the time from the low-to-high transition of RESET until the input receivers are fully enabled, the design must ensure that the

19、 outputs will remain low.Package options include plastic thin shrink small-outline package (MO-153) and 56-pin Very Fine Pitch Quad Flat No-Lead Package (MO-220).JEDEC Standard No. 82-13APage 22 Device standard (contd)2.2 Pinout figuresFigure 1 64-pin TSSOP and 56-pin VFQFPN packages and pinouts1234

20、56789101112131415161718192021222324646362616059585756555453525150494847464544434241VDDQGNDD13VDDVDDQGNDD11D10D9GNDD7VDDQVDDVREFGNDD5D4Q13AQ12AQ9AVDDQGNDTOP VIEW25262728293031324039383736353433D12D8RESETGNDCKCKD6D3GNDVDDQVDDD2D1GNDVDDQQ11AQ10AQ8AQ7AQ6AQ5AQ4AQ3AQ2AGNDQ1AQ13BVDDQQ12BQ11BQ10BQ9BQ8BQ7BQ6

21、BGNDVDDQQ5BQ4BQ3BQ2BQ1B56-pin VFQFPN (MO-220, VLLD2, E2=5.2mm nominal, D2=4.5mm nominal)JEDEC Standard No. 82-13APage 32 Device standard (contd)2.3 Terminal functions2.4 Function tableTable 1 Terminal functionsTerminalnameDescriptionElectricalcharacteristicsQ1Q13 Data outputPC1600, PC2100, PC2700SST

22、L_2, Class II outputPC3200SSTL_2, Class II outputGND Ground Ground inputVDDQOutput-stage drain power voltagePC1600, PC2100, PC2700 2.5-V nominalPC3200 2.6-V nominalVDDLogic power voltagePC1600, PC2100, PC2700 2.5-V nominalPC3200 2.6-V nominalRESETAsynchronous reset input resets registers and disable

23、s data and clock differential-input receiversLVCMOS inputVREFInput reference voltagePC1600, PC2100, PC2700 1.25-V nominalPC3200 1.30-V nominalCK Positive master clock input Differential inputCK Negative master clock input Differential inputD1D13Data input clocked in on the crossing of the rising edg

24、e of CK and the falling edge of CKSSTL_2 inputTable 2 Function table (each flip flop)InputsQ OutputsRESET CK CK DHLLH HHH L or H L or H XQ0LX or FloatingX or FloatingX or FloatingLJEDEC Standard No. 82-13APage 42 Device standard (contd)2.5 Logic diagramFigure 2 Logic diagram (positive logic)2.6 Abso

25、lute maximum ratingsTable 3 Absolute maximum ratings over operating free-air temperature range (see Note 1)Supply voltage range, VDDor VDDQ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 3.6 VInput voltage range, VI(See Notes 2 and 3) . . . . . . . . . . . . . . .

26、. . . . . . . . . . 0.5 V to VDD+ 0.5 VOutput voltage range, VO(See Notes 2 and 3) . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VDDQ+ 0.5 VInput clamp current, IIK(VIVDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 mAOutput clamp current, IOK(VOVDDQ) . . . . . . .

27、 . . . . . . . . . . . . . . . . . . . . . . . 50 mAContinuous output current, IO(VO= 0 to VDDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 mAContinuous current through each VDD, VDDQor GND . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mAStorage temperature range,

28、TSTG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 C to 150 CNOTE 1 Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other cond

29、itions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 2 The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings

30、are observed.NOTE 3 This value is limited to 3.6 V maximum.1DC1R16Q1A5148494535RESETCKCKVREFD1To 12 Other Channels32Q1BJEDEC Standard No. 82-13APage 52 Device standard (contd)2.7 Recommended operating conditionsNOTE The RESET input of the device must be held at VDDor GND to ensure proper device oper

31、ation. The differential inputs must not be floating, unless RESET is low.Table 4 Recommended operating conditions (see Note)Min Nom Max UnitVDDSupply voltageVDDQ2.7 VVDDQOutput supply voltagePC1600-2700 2.3 2.7 VPC3200 2.5 2.7 VVREFReference voltage(VREF= VDDQ/ 2)PC1600-2700 1.15 1.25 1.35 VPC3200 1

32、.25 1.30 1.35VTTTermination voltageVREF 40 mV VREFVREF+ 40 mVVVIInput voltage 0VDDVVIHAC high-level input voltage Data inputsVREF+ 310 mVVVILAC low-level input voltage Data inputsVREF 310 mVVVIHDC high-level input voltage Data inputsVREF+ 150 mVVVILDC low-level input voltage Data inputsVREF 150 mVVV

33、IHHigh-level input voltage RESET 1.7 VVILLow-level input voltage RESET 0.7 VVICRCommon-mode input range CK, CK 0.97 1.53 VVIDDifferentail input voltage CK, CK 360 mVIOHHigh-level output current 20mAIOLLow-level output current 20TAOperating free-air temperature 0 70 CJEDEC Standard No. 82-13APage 62

34、Device standard (contd)2.8 DC specificationsTable 5 Electrical characteristics over recommended operating free-air temperature range for PC1600, PC2100 and PC2700PARAMETER TEST CONDITIONSVDDMIN TYP MAX UNITVIKII= 18 mA2.3 V 1.2 VVOHIOH= 100 A2.3 to 2.7 VVDD0.2VIOH= 16 mA2.3 V 1.95VOLIOL= 100 A2.3 to

35、 2.7 V 0.2VIOL= 16 mA2.3 V 0.35IIAll inputsVI= VDDor GND2.7 V 5 AIDDStatic standby RESET= GNDIO= 02.7 V0.01mAStatic operatingRESET = VDD,VI= VIH(AC)or VIL(AC)IDDDDynamic operating clock onlyRESET = VDD,VI= VIH(AC)or VIL(AC),CK and CK switching 50% duty cycleIO= 02.7 VA/clock MHzDynamic operating per

36、 each data inputRESET = VDD,VI= VIH(AC)or VIL(AC),CK and CK switching 50% duty cycle. One data input switching at half clock frequency, 50% duty cycle.A/clock MHz/data inputCiData inputsVI= VREF 310 mV2.5 V2.5 3.5pFCK and CK VICR= 1.25 V, VI(PP)= 360 mV2.5 3.5RESET VI= VDDor GNDThe vendor must suppl

37、y this value for full device description.JEDEC Standard No. 82-13APage 72 Device standard (contd)2.8 DC specifications (contd)Table 6 Electrical characteristics over recommended operating free-air temperature range for PC3200PARAMETER TEST CONDITIONSVDDMIN TYP MAX UNITVIKII= 18 mA2.5 V 1.2 VVOHIOH=

38、100 A2.5 to 2.7 VVDD0.2VIOH= 16 mA2.5 V 1.95VOLIOL= 100 A2.5 to 2.7 V 0.2VIOL= 16 mA2.5 V 0.35IIAll inputsVI= VDDor GND2.7 V 5 AIDDStatic standby RESET= GNDIO= 02.7 V0.01mAStatic operatingRESET = VDD,VI= VIH(AC)or VIL(AC)IDDDDynamic operating clock onlyRESET = VDD,VI= VIH(AC)or VIL(AC),CK and CK swi

39、tching 50% duty cycleIO= 02.7 VA/clock MHzDynamic operating per each data inputRESET = VDD,VI= VIH(AC)or VIL(AC),CK and CK switching 50% duty cycle. One data input switching at half clock frequency, 50% duty cycle.A/clock MHz/data inputCiData inputsVI= VREF 310 mV2.6 V2.5 3.5pFCK and CK VICR= 1.30 V

40、, VI(PP)= 360 mV2.5 3.5RESETVI= VDDor GNDThe vendor must supply this value for full device description.JEDEC Standard No. 82-13APage 82 Device standard (contd)2.9 Timing requirementsNOTE 1 Data inputs must be low a minimum time of tactmax, after RESET is taken highNOTE 2 Data and clock inputs must b

41、e held at valid levels (not floating) a minimum time of tinactmax, after RESET is taken low.NOTE 3 For data signal input slew rate 1 V/ns.NOTE 4 For data signal input slew rate 0.5 V/ns and 1 V/ns.NOTE 5 CK, CK signals input slew rates are 1 V/ns.Table 7 Timing requirements over recommended operatin

42、g free-air temperature range.PC1600, PC2100, PC2700PC3200UNITVDD= 2.5 V 0.2 V VDD= 2.6 V 0.1 VMIN MAX MIN MAXfclockClock frequency 200 220 MHztwPulse duration, CK, CK high or low 2.5 2.5 nstactDifferential inputs active time (see Note 1)22 22 nstinactDifferential inputs inactive time (see Note 2)22

43、22 nstsuSetup time, fast slew rate (See Notes 3 and 5)Data before CK , CK 0.65 0.65 nsSetup time, slow slew rate (See Notes 4 and 5)0.75 0.75 nsthHold time, fast slew rate (See Notes 3 and 5)Data after CK , CK 0.75 0.75 nsHold time, slow slew rate (See Notes 4 and 5)0.9 0.9 nsThis parameter is not n

44、ecessarily production tested.JEDEC Standard No. 82-13APage 92 Device standard (contd)2.10 AC specificationsNOTE 6 The Simultaneous Switching specification is guaranteed by Characterization.NOTE 7 Measured with reference load, see Figure 4. tPDMis vendor specific. It is not required for compliant dev

45、ices that this parameter is specified.NOTE 8 The Simultaneous Switching specification is guaranteed by Characterization.NOTE 9 Measured with reference load, see Figure 4. tPDMis vendor specific. It is not required for compliant devices that this parameter is specified.Table 8 Switching characteristi

46、cs over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)PARAMETERFROM(INPUT)TO(OUTPUT)PC1600, PC2100, PC2700UNITVDD= 2.5 V 0.2 VMIN MAXfmax200 MHztpdCK and CK Q 1.1 2.6 nstpdss (see Note 6)CK and CK Q2.9tPHLRESET Q5tPDMCK - CK Q see Note 7 nsTable 9 Switching

47、characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)PARAMETERFROM(INPUT)TO(OUTPUT)PC3200UNITVDD= 2.6 V 0.1 VMIN MAXfmax220 MHztpdCK and CK Q64-pin TSSOP 1.1 2.2 ns56-pin VFQFPN 1.1 1.8 nstpdss (see Note 8)CK and CK Q64-pin TSSOP 2.5 ns56-pin V

48、FQFPN 2.0 nstPHLRESET Q5tPDMCK - CK Q see Note 9 nsJEDEC Standard No. 82-13APage 103 Output buffer characteristics3.1 Voltage vs. current (V/I)The following table describes output-buffer Voltage vs. Current (V/I) characteristics that are sufficient to meet the requirements of registered DDR DIMM per

49、formance and timings. These characteristics are not necessarily production tested but can be guaranteed by design or characterization. Compliance with these curves is not mandatory if it can be adequately demonstrated that alternative characteristics meet the requirements of the registered DDR DIMM application.Table 10 Output buffer voltage vs. current (V/I) characteristicsVoltage(V)Pull-down Pull-dpI(mA) I(mA) I(mA) I(mA)MIN MAX MIN MAX0000-00.1 5 18 -5 -1