JEDEC JESD82-1A-2004 Definition of CVF857 PLL Clock Driver for Registered PC1600 PC2100 PC2700 a n d PC3200 DIMM Applications《PC1600 PC2100 PC2700和PC3200 DIMM应用软件CVF857相同步逻辑时钟驱动器的定.pdf

1、JEDEC SOLID STATE TECHNOLOGY ASSOCIATIONJESD82-1AMAY 2004JEDECSTANDARDDefinition of CVF857 PLL Clock Driverfor Registered PC1600, PC2100, PC2700 and PC3200 DIMM Applications NOTICEJEDEC standards and publications contain material that has been prepared, reviewed, and approvedthrough the JEDEC Counci

2、l level and subsequently reviewed and approved by the EIA General Counsel.JEDEC standards and publications are designed to serve the public interest through eliminatingmisunderstandings between manufacturers and purchasers, facilitating interchangeability andimprovement of products, and assisting th

3、e purchaser in selecting and obtaining with minimum delay theproper product for use by those other than JEDEC members, whether the standard is to be used eitherdomestically or internationally.JEDEC standards and publications are adopted without regard to whether or not their adoption mayinvolve pate

4、nts or articles, materials, or processes. By such action JEDEC does not assume any liability toany patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards orpublications.The information included in JEDEC standards and publications represents a sound approach

5、to productspecification and application, principally from the solid state device manufacturer viewpoint. Within theJEDEC organization there are procedures whereby a JEDEC standard or publication may be furtherprocessed and ultimately become an EIA standard.No claims to be in conformance with this st

6、andard may be made unless all requirements stated in thestandard are met.Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication shouldbe addressed to JEDEC Solid State Technology Association, 2500 Wilson Boulevard, Arlington, VA22201-3834, (703)907-7559 or

7、 www.jedec.org.Published byJEDEC Solid State Technology Association 20042500 Wilson BoulevardArlington, VA 22201-3834This document may be downloaded free of charge, however JEDEC retains the copyright on this material. By downloading this file the individual agrees not to charge for or resell the re

8、sulting material.Price: Please refer to the current Catalogue of JEDEC Standards and Publications online at: http:/www.jedec.org/catalog/catalog.cfmPrinted in the U.S.A.All rights reservedPLEASE! DONT VIOLATE THE LAW! This document is copyrighted by JEDEC and may not be reproduced without permission

9、. Organizations may obtain permission to reproduce a limited number of copies through entering into a license agreement. For information, contact: JEDEC Solid State Technology Association 2500 Wilson Boulevard Arlington, Virginia 22201-3834 or call (703) 907-7559 JEDEC Standard No. 82-1APage 1STANDA

10、RD FOR DEFINITION OF CVF857 PLL CLOCK DRIVERFOR REGISTERED PC1600, PC2100, PC2700 AND PC3200 DIMM APPLICATIONS(From JEDEC Board Ballot JCB-03-86, formulated under the cognizance of the JC-40 Committee on Digital Logic.)1 ScopeThis standard defines standard specifications of dc interface parameters,

11、switching parameters, and test loading for definition of a CVF857 PLL clock device for registered PC1600, PC2100, PC2700 and PC3200 DIMM applications.The purpose is to provide a standard for a CVF857 PLL clock device, for uniformity, multiplicity of sources, elimination of confusion, ease of device

12、specification, and ease of use. 2 Terms and definitions (for the purpose of this document)CI() Delta input capacitance.3 Device standard3.1 DescriptionThis PLL Clock Buffer is specified for a VDDQ of 2.5 V (PC1600, PC2100 and PC2700) and 2.6 V (PC3200); an AVDDof 2.5 V (PC1600, PC2100 and PC2700) an

13、d 2.6 V (PC3200); and differential data input and output levels. Package options include plastic 48-pin Thin Shrink Small-Outline Package (TSSOP) and 40-pin Very Fine Pitch Quad Flat No-Lead Package (VFQFPN).The device is a zero delay buffer that distributes a differential clock input pair (CK, CK)

14、to ten differential pair of clock outputs (Y0:9, Y0:9) and one differential pair feedback clock outputs (FBOUT, FBOUT). The clock outputs are controlled by the input clocks (CK, CK), the feedback clocks (FBIN, FBIN), the 2.5-V LVCMOS input (PWRDWN) and the Analog Power input (AVDD). When input PWRDW

15、N is low while power is applied, the receivers are disabled, the PLL is turned off and the differential clock outputs are 3-stated. When AVDDis grounded, the PLL is turned off and bypassed for test purposes.When the input frequency is less than approximately 20 MHz, which is below the operating freq

16、uency of the PLL, the device will enter a low power mode. An input frequency detection circuit on the differential inputs, independent from the input buffers, will detect the low frequency condition and perform the same low power features as when the PWRDWN input is low. When the input frequency inc

17、reases to greater than approximately 20 MHz, the PLL will be turned back on, the inputs and outputs will be enabled and PLL will obtain phase lock between the feedback clock pair (FBIN, FBIN) and the input clock pair (CK, CK).The PLL in the CVF857 clock driver uses the input clocks (CK, CK) and the

18、feedback clocks (FBIN, FBIN) to provide high-performance, low-skew, low-jitter output differential clocks (Y0:9, Y0:9). The CVF857 is also able to track Spread Spectrum Clocking (SSC) for reduced EMI.The CVF857 is characterized for operation from 0oC to 70 oC.JEDEC Standard No. 82-1APage 23 Device s

19、tandard (contd)3.2 Pinout figureFigure 1 48-Pin TSSOP and 40-pin HP-VFQFP-N package pinouts3.3 Terminal functionsTable 1 Terminal FunctionsTerminalNameDescriptionElectricalCharacteristicsAGND Analog Ground GroundAVDDAnalog powerPC1600, PC2100, PC2700 2.5 V nominalPC3200 2.6 V nominalCK Clock input D

20、ifferential inputCK Complementary clock input Differential inputFBIN Feedback clock input Differential inputFBIN Complementary feedback clock input Differential inputFBOUT Feedback clock output Differential outputFBOUT Complementary feedback clock output Differential outputPWRDWN Power down LVCMOS i

21、nputGND Ground GroundVDDQLogic and output powerPC1600, PC2100, PC2700 2.5 V nominalPC3200 2.6 V nominalY0:9 Clock outputs Differential outputsY0:9 Complementary clock outputs Differential outputsTOP VIEWVDDQ123456789101112131415161718192021222324484746454443424140393837353634333231302928272625FBOUTG

22、NDVDDQGNDGNDVDDQFBINFBINPWRDWNVDDQGNDGNDY9Y8Y8FBOUTY7Y7Y6Y6Y5Y5VDDQY9GNDGNDVDDQGNDY0Y0Y1Y1VDDQVDDQGNDCKCKY2Y2GNDY3Y3Y4Y4AGNDVDDQAVDDY0 Y0 Y5Y1 Y1 VDDQY5 VDDQY6 Y640 31PWRDWNFBINFBINY7Y7VDDQVDDQFBOUTFBOUT3021Y9Y9Y4 Y8Y8VDDQY4VDDQY3Y32011VDDQCKCKGNDAGNDAVDDVDDQY2Y2GND101VDDQGND40-pin HP-VFQFP-N (6.0x6

23、.0mm Body Size, 0.5mmPitch, M0#220, variation VJJD-2, E2=D2=2.9mm+/- 0.15mm) package pinouts48-pin TSSOP (MO-153-ED)JEDEC Standard No. 82-1APage 33 Device standard (contd)3.4 Function tableNOTE 1 AVDDNominal is 2.5 V for PC1600, PC2100 and PC2700; and 2.6 V for PC3200.3.5 Logic diagramFigure 2 Logic

24、 diagram (positive logic)Table 2 Function table (see Note 1)Inputs OutputsPLLAVDDPWRDWN CK CK YYFBOUT FBOUTGND H L H L LH Bypassed/OffGND H H L HL L Bypassed/OffXLLHZZZZOfHLZZfNominal H L H LHLHOnNominalH H L HLHL OnoinalX VDDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

25、 . . . . . . 50 mAOutput clamp current, IOK(VOVDDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mAContinuous output current, IO(VO= 0 to VDDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mAContinuous current through each AVD

26、D, VDDQor GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mAStorage temperature range, TSTG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 C to 150 CNOTE 2 Stresses beyond those listed under “absolute maximum ratings

27、” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may af

28、fect device reliability. NOTE 3 The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.NOTE 4 This value is limited to 3.6 V maximum.3.7 Recommended operating conditionsNOTE 5 The PLL is turned off and bypassed for test purposes when AVDDis gr

29、ounded. During this test mode, VDDQremains within the recommended operationing conditions and no timing parameters are guaranteed.NOTE 6 VIDis the magnitude of the difference between the input level on CK and the input level on CK.NOTE 7 AVDD VDDQwith a tolerance of 0.12 V.Table 4 Recommended operat

30、ing conditionsMin Nom Max UnitVDDQOutput supply voltagePC1600-27002.32.5 2.7 VPC3200 2.5 2.6 2.7 VAVDDSupply voltage See Note 5,7VDDQ-0.12 VDDQ2.7 VVILLow-level input voltage PWRDWN 0.3 0.7 VVIHHigh-level input voltage PWRDWN 1.7 VDDQ+ 0.3 VIOHHigh-level output current 12 mAIOLLow-level output curre

31、nt 12 mAVIXInput differential-pair cross voltage (VDDQ/2) 0.2 (VDDQ/2) + 0.2 VVINInput voltage level 0.3VDDQ+ 0.3VVIDInput differential voltage,See Note 6DC 0.36VDDQ+ 0.6VAC 0.70VDDQ+ 0.6VTAOperating free-air temperature 0 70 CJEDEC Standard No. 82-1APage 53 Device standard (contd)3.8 DC specificati

32、onsNOTE 8 Total IDD= IDDQ+IADD= FCK* CPD* VDDQ, solving for CPD= (IDDQ+IADD)/(FCK*VDDQ) where FCKis the input Frequency, VDDQis the power supply and CPDis the Power Dissipation Capacitance.Table 5 Electrical characteristics over recommended operating free-air temperature range for PC1600, PC2100 and

33、 PC2700 PARAMETER TEST CONDITIONSAVDD, VDDQMIN TYP MAX UNITVIKAll inputs II= 18 mA2.3 V 1.2 VVOHHigh output voltageIOH= 100 A2.3 V to 2.7 VVDDQ0.1VIOH= 12 mA 2.3 V 1.7VOLLow output voltageIOL= 100 A2.3 V to 2.7 V 0.1VIOL= 12 mA2.3 V 0.6IICK, FBIN VI= VDDQor GND 2.7 V 10APWRDWN VI= VDDQor GND 2.7 V 1

34、0IDDPDStatic supply current, IDDQ+ IADDCK and CK = 0 MHz andPWRDWN = Low100 200 AIDDQDynamic supply current, see Note 8 for CPDcalculationCK and CK = 170 MHz,all outputs are open (not connected to a PCB)2.7 V 200 300 mAIADDDynamic supply current, see Note 8 for CPDcalculationCK and CK = 170 MHz 2.7

35、V 9 12 mACICK and CK VI= VDDQor GND, Part-to-Part variation (CI) is less than 1pF2.5 V23.5pFFBIN and FBINCI()CK and CK VI= VDDQor GND 0.25 0.25FBIN and FBIN VI= VDDQor GND 0.25 0.25JEDEC Standard No. 82-1APage 6Table 6 Electrical characteristics over recommended operating free-air temperature range

36、for PC3200NOTE 9 Total IDD= IDDQ+IADD= FCK* CPD* VDDQ, solving for CPD= (IDDQ+IADD)/(FCK*VDDQ) where FCKis the input Frequency, VDDQis the power supply and CPDis the Power Dissipation Capacitance.PARAMETER TEST CONDITIONSAVDD, VDDQMIN TYP MAX UNITVIKAll inputs II= 18 mA2.5 V 1.2 VVOHHigh output volt

37、ageIOH= 100 A 2.5 V to 2.7 V VDDQ0.1VIOH= 12 mA2.5 V 1.7VOLLow output voltageIOL= 100 A2.5 V to 2.7 V 0.1VIOL= 12 mA 2.5 V 0.6IICK, FBIN VI= VDDQor GND 2.7 V 10APWRDWNVI= VDDQor GND2.7 V 10IDDPDStatic supply current, IDDQ+ IADDCK and CK = 0 MHz andPWRDWN = Low100 200 AIDDQDynamic supply current, see

38、 Note 9 for CPDcalculationCK and CK = 200 MHz,all outputs are open (not connected to a PCB)2.7 V 200 300 mAIADDDynamic supply current, see Note 9 for CPDcalculationCK and CK = 200 MHz 2.7 V 9 12 mACICK and CK VI= VDDQor GND, Part-to-Part variation (CI) is less than 1pF2.6 V23.5pFFBIN and FBINCI()CK

39、and CK VI= VDDQor GND 0.25 0.25FBIN and FBINVI= VDDQor GND0.25 0.25JEDEC Standard No. 82-1APage 73 Device standard (contd)3.9 Timing requirementsNOTE 10 The PLL must be able to handle spread spectrum induced skew.NOTE 11 Operating clock frequency indicates a range over which the PLL must be able to

40、lock, but in which it is not required to meet the other timing parameters. (Used for low speed system debug.)NOTE 12 Application clock frequency indicates a range over which the PLL must meet all timing parameters.NOTE 13 Stabilization time is the time required for the integrated PLL circuit to obta

41、in phase lock of its feedback signal to its reference signal after power up. During normal operation, the stabilization time is also the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal when the input clock frequency falls below 20 MHz,

42、 entered the power-down mode and later increased above 20 MHz.Table 7 Timing requirements over recommended operating free-air temperature range.DESCRIPTION DIMMAVDD, VDDQMIN MAX UNITfCKOperating clock frequency (see Notes 10 and 11)PC1600-2700 2.5 V 0.2 V 60 170MHzPC3200 2.6 V 0.1 V 60 220Applicatio

43、n clock frequency (see Notes 10 and 12)PC1600-2700 2.5 V 0.2 V 95 170MHzPC3200 2.6 V 0.1 V 95 220tDCInput clock duty cyclePC1600-2700 2.5 V 0.2 V 40 60%PC3200 2.6 V 0.1 V 40 60tLStabilization time (see Note 13)PC1600-2700 2.5 V 0.2 V 100sPC3200 2.6 V 0.1 V 100JEDEC Standard No. 82-1APage 83 Device s

44、tandard (contd)3.10 AC specificationsTable 8 Switching characteristics over recommended operating free-air temperature range(unless otherwise noted) (Figures 3 and 4)NOTE 14 Static Phase Offset does not include Jitter.NOTE 15 Period Jitter and Half-Period Jitter specifications are separate specifica

45、tions that must be met independently of each other.NOTE 16 The Output Slew Rate is calculated using the load shown in Figure 5 and measured at the 20% and 80% voltage points, see Figure 11.NOTE 17 The SSC requirements meets the Intel PC100 SDRAM Registered DIMM specification. NOTE 18 VOXspecified at

46、 the DRAM clock input or the test load, see Figure 4PARAMETER DESCRIPTION DIAGRAMPC1600, PC2100, and PC2700UNITAVDD, VDDQ= 2.5 V 0.2 VMIN Nom MAXtjit(cc) Cycle-to-cycle period jitter see Figure 6 75 75 pst() Static phase offset (see Note 14) see Figure 7 50 0 50 pstsk(o) Output clock skew see Figure

47、 8 100 pstjit(per) Period jitter (see Note 15) see Figure 9 75 75 pstjit(hper) Half-period jitter (see Note 15) see Figure 10 100 100 psslr(i)Input clock slew rate, measured single-endedsee Figure 11 1.0 4.0 V/nsslr(o)Output clock slew rate, measured single-ended (see Note 16)see Figure 11 1.0 2.0 V

48、/nsVOXOutput differential-pair cross- voltage, See Note 18 and Figure 4(VDDQ/2) 0.15(VDDQ/2) + 0.15VThe PLL on the CVF857 must be capable of meeting all the above test parameters while supporting SSC synthesizers with the following parameters: SSC modulation frequency 30.00 50.00 kHzSSC clock input

49、frequency deviation 0.00 0.50 %CVF857 PLL designs should target the values below to meet the 200 ps maximum of SSC induced skew:PLL loop bandwidth (see Note 17) 2.0 MHzPhase angle 0.031 degreesJEDEC Standard No. 82-1APage 93 Device standard (contd)Table 9 Switching characteristics over recommended operating free-air temperature range(unless otherwise noted) (Figures 3 and 4)NOTE 19 Static Phase Offset does not include Jitter.NOTE 20 Period Jitter and Half-Period Jitter specific