1、 2500 Wilson Boulevard Arlington, Virginia 22201-3834 (703) 907-7559 FAX (703) 907-7583 July 20, 2001 ANNOUNCEMENT AVAILABILITY OF JEDEC STANDARD The JEDEC Solid State Technology Association (JEDEC) announces the release of JEDEC Standard No. 82-2 (JESD82-2), “Standard For Description of a 3.3 V, 18
2、-Bit, LVTTL I/O Register for PC133 Registered DIMM applications“. This standard defines the register support devices needed for standard height and low profile registered PC133 SDRAM DIMM modules. The objective of the standard is to clearly define the functionality, pinout and electrical characteris
3、tics required for this type of SDRAM module. JESD82-2 was developed by the JC-40 Committee on Digital Logic under the chairmanship of Mr. Stan Hronik of Integrated Device Technology, Inc. and the authorship of Mr. Jim Boomer of Fairchild Semiconductor, and with support from the JC-42.5 Memory Module
4、 Committee. To obtain copies of JESD82-2 ($38.00 ea.), contact Global Engineering Documents, 15 Inverness Way East, Englewood, CO 80112-5704 or call U.S.A. and Canada 1-800-854-7179, International (303) 397-7956. To download this document for free, access the JEDEC web site at www.jedec.org. JEDEC S
5、TANDARD Description of a 3.3 V, 18-Bit, LVTTL I/O Register for PC133 Registered DIMM Applications JESD82-2 JULY 2001 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors l
6、evel and subsequently reviewed and approved by the EIA General Counsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting th
7、e purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. JEDEC standards and publications are adopted without regard to whether or not their adoption may involve
8、patents or articles, materials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or publications. The information included in JEDEC standards and publications represents a sound ap
9、proach to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby an JEDEC standard or publication may be further processed and ultimately become an ANSI/EIA standard. No claims to be in conform
10、ance with this standard may be made unless all requirements stated in the standard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC Solid State Technology Association, 2500 Wilson Boulevard, Arlington, VA 22201-3
11、834, (703)907-7559 or www.jedec.org Published by JEDEC Solid State Technology Association 2001 2500 Wilson Boulevard Arlington, VA 22201-3834 This document may be downloaded free of charge; however JEDEC retains the copyright on this material. By downloading this file the individual agrees not to ch
12、arge for or resell the resulting material. PRICE: Please refer to the current Catalog of JEDEC Engineering Standards and Publications or call Global Engineering Documents, USA and Canada 1-800-854-7179, International (303) 397-7956 Printed in the U.S.A. All rights reserved PLEASE! DONT VIOLATE THE L
13、AW! This document is copyrighted by the Electronic Industries Alliance and may not be reproduced without permission. Organizations may obtain permission to reproduce a limited number of copies through entering into a license agreement. For information, contact: JEDEC Solid State Technology Associati
14、on 2500 Wilson Boulevard Arlington, Virginia 22201-3834 or call (703) 907-7559 JEDEC Standard No. 82-2 Page 1 STANDARD FOR DESCRIPTION OF A 3.3 V, 18-BIT, LVTTL I/O REGISTER FOR PC133 REGISTERED DIMM APPLICATIONS (From JEDEC Board Ballot JCB-00-58, formulated under the cognizance of the JC-40 Commit
15、tee on Digital Logic.) 1 Scope This standard defines dc and ac interface parameters and test loading for registers targeted for use in the PC133 Registered DIMM specification. The logical functionality of the device is based on the 16835/162835 and 16834/162834 functions found in multiple families o
16、f digital logic devices. AC performance requirements are as specified in the PC133 Registered DIMM specification. The purpose is to provide a standard for an 18-bit register compatible with the requirements of the PC133 Registered DIMM specification operating with a nominal supply voltage (VDD) of 3
17、.3 V. 2 Terms and definitions Prefixes “54“ or “74” immediately preceding family name indicate the operating temperature range. For example, 54XXX refers to the Military (MIL) version of devices which are specified over the temperature range of 55 C to 125 C. 74XXX refers to the Commercial (COML) ve
18、rsion of devices which are specified over 40 C to 85 C. PC133: A JEDEC designation for systems with a 133 MHz Front Side Bus using SDRAM main memory technology running at a nominal clock frequency of a 133 MHz. JEDEC Standard No. 82-2 Page 2 3 Device standard 3.1 Description The 18-bit universal reg
19、ister is designed to operate with a 3.0-V to 3.6-V supply voltage. All inputs support operation with standard LVTTL interface levels. This includes data inputs, clock inputs and control inputs. Device outputs meet the requirements of the PC133 Registered DIMM specification. The device functions as d
20、efined supports latched, registered and flow through modes of operation. The PC133 Specification requires only registered mode. Only ac specifications relevant to the register mode of operation are shown in this document. Package is a 56 thin shrink small-outline package as defined by JEDEC Publicat
21、ion, JEP95, MO-153. JEDEC Standard No. 82-2 Page 3 3 Device standard (contd) 3.2 Pinout figure NC 1 56 GND NC 2 55 NC Y1 3 54 A1GND 4 53 GND Y2 5 52 A2Y3 6 51 A3VDD 7 50 VDDY4 8 49 A4Y5 9 48 A5Y6 10 47 A6GND 11 46 GND Y7 12 45 A7Y8 13 44 A8Y9 14 43 A9Y10 15 42 A10Y11 16 41 A11Y12 17 40 A12GND 18 39
22、GND Y13 19 38 A13Y14 20 37 A14Y15 21 36 A15VDD 22 35 VDDY16 23 34 A16Y17 24 33 A17GND 25 32 GND Y18 26 31 A18OE 27 30 CLK LE 28 29 GND NC 1 56 GND NC 2 55 NC Y1 3 54 A1GND 4 53 GND Y2 5 52 A2Y3 6 51 A3VDD 7 50 VDDY4 8 49 A4Y5 9 48 A5Y6 10 47 A6GND 11 46 GND Y7 12 45 A7Y8 13 44 A8Y9 14 43 A9Y10 15 42
23、 A10Y11 16 41 A11Y12 17 40 A12GND 18 39 GND Y13 19 38 A13Y14 20 37 A14Y15 21 36 A15VDD 22 35 VDDY16 23 34 A16Y17 24 33 A17GND 25 32 GND Y18 26 31 A18OE 27 30 CLK LE 28 29 GND Figure 1a 56 Pin Dual Inline Pinout16835/162835 Function Figure 1b 56 Pin Dual Inline Pinout 16834/162834 Function JEDEC Stan
24、dard No. 82-2 Page 4 3 Device standard (contd) 3.3 Terminal functions Table 1 Terminal Function Terminal Name Descriptions Electrical Characteristics Y1-Y18 Data Outputs LVCMOS A1-A18 Data Inputs LVTTL LE or LE Latch Enable Control Input LVTTL OE Output Enable 0=Enabled 1 = Disabled LVTTL CK Rising
25、edge triggered clock input signal LVTTL VDD Positive Supply Voltage 3.3 V Nominal GND Ground Ground Supply3.4 Function table Table 2a 16835/162835 Function Table (each data bit) Table 2b 16834/162834 Function Table (each data bit) Inputs Output Inputs Output OE LE CK A Y OE LELE CK A Y H X X X Z H X
26、 X X Z L H X L L L L X L L L H X H H L L X H H L L L L L H L L L L H H L H H H L L H X Y L H H X Y0L L L X Y L H L X Y0L = Logic LOW H = Logic HIGH Z = HIGH-Z (high impedance) X = Dont Care (But not floating) = Rising Edge Signal Y0= Previous State of Y JEDEC Standard No. 82-2 Page 5 3 Device standa
27、rd (contd) 3.5 Logic Diagram A1LECKY1OE1DC1CKTo 17 Other ChannelsFigure 2A 16835/162835 Logic diagram (positive logic) OETo 17 Other ChannelsA1CKY11DC1CKLEFigure 2B 16834/162834 Logic diagram (positive logic) JEDEC Standard No. 82-2 Page 6 3 Device standard (contd) 3.6 Absolute maximum ratings Table
28、 3 Absolute maximum ratings Supply voltage range, (VDD) -0.5 V to 4.6 V DC Input voltage range, (VI) -0.5 V to 4.6 V DC Output voltage range (VO) -0.5 V to 4.6 V Input clamp current (IIK) -50 mA Output clamp current (IOK) 50 mA Storage temperature range (TSTG) -65 C to 150 C VDD, GND current / pin (
29、IDDor IGND) 100 mA NOTE 1 Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under these conditions is not implied. NOTE 2 Un
30、der transient conditions these ratings may be exceeded as defined elsewhere in this specification. 3.7 Recommended operating conditions Table 4 Recommended operating conditions Standard Range Symbol Parameter Min Typ Max VDDSupply Voltage 3.0 3.3 3.6 V VINVoltage Applied to input pins -0.3 3.6 V out
31、puts enabled 0 VDDV VOUTVoltage applied to output or I/O pins. outputs high-Z 0 VDDV TAOperating free-air temperature 0 70 C JEDEC Standard No. 82-2 Page 7 3 Device standard (contd) 3.8 DC specifications Table 5 DC specifications*Symbol Parameter Condition VDD (V) Min Typ Max Units VIHHIGH-level inp
32、ut voltage 3.0-3.6 2.0 V VILLOW level input voltage 3.0-3.6 0.8 V VOHHIGH-level output voltage IOH= -12 mA, VIH= 2.0 V 3.0 2.2 V VOLLow-level output voltage IOL= 12 mA, VIL= 0.8 V 3.0 0.8 Input leakage current VI = VDD or GND 3.0-3.6 10.0 A Off-state leakage current (see note 2) VO= VDDor GND, OE =
33、VDD20 A IDDQuiescent Supply Current VI= VDDor GND, IO= 0 40 A * Parameters are characterized over recommended operating conditions. 3.9 Critical register specifications Table 6 Critical register specifications* Symbol Parameter Condition VDD (V) Min Typ Max Units tPD* Propagation Delay (CK to Y) RL
34、= 500 , CL=50 pF 3.0-3.6 1.4 3.5 ns tPD* Propagation Delay (CK to Y) RL = 500 , CL=30 pF 3.0-3.6 0.7 2.5 ns tSSetup time. (A before CK) 3.0-3.6 1.0 ns tHHold time. (A after CK) 3.0-3.6 0.6 ns CIClock input Capacitance 3.0-3.6 3.3 4.0 6.0 pF * Parameters are characterized over recommended operating c
35、onditions. * The tPDvalue in this table would equate to the Time-to-Vm delay described in the post register timing specifications of the PC133 registered DIMM Specification. The first value applies to DIMMs with nine SDRAM loads per register output, and the second to DIMMs with eighteen SDRAM loads
36、per register output. These values should serve as only an initial starting point, as the critical timing closure is dependent on the DIMM net structure and the distributed load. JEDEC Standard No. 82-2 Page 8 4 Test circuit and switching waveforms DUTRLCLRL2 x VDDOpenGNDPulseGeneratorRTFigure 3 Test
37、 circuit Test circuit component values: RL= Load Resistor CL = Load Capacitance and includes probe and jig capacitance RT= Termination resistance should be equal to ZOUTof Pulse Generator VIN= 0 to VDD tr= tf 2.0 ns (10% to 90%) unless otherwise specified. Parameter Tested Switch Position tPLHOpen t
38、PHLOpen tPZHGND tPZL2x VDDtPHZGND tPLZ2x VDDJEDEC Standard No. 82-2 Page 9 4 Test circuit and switching waveforms (contd) Propagation Delay MeasurementAnCKYntPLHtPHLVIHVILVIHVILVOHVOLSetup Time MeasurementsAnCKYntStSVIHVILVIHVILVOHVOLHold Time MeasurementsAnCKYntHtHVIHVILVIHVILVOHVOLFigure 4 Switching waveforms 5 Reference to other applicable JEDEC standards and publications JESD52, Standard for Description of Low Voltage TTL-Compatible CMOS Logic Devices, November 1995. JESD21-C (all parts), Configuration for Solid State Memories. JEDEC Standard No. 82-2 Page 10
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