JEDEC JESD82-2000 Definition of CDCV857 PLL Clock Driver for Registered DDR DIMM Applications《注册的DDR DIMM应用软件CDCV857相同步逻辑时钟驱动器的定义》.pdf

1、JEDECSTANDARDDefinition of CDCV857 PLL ClockDriver for Registered DDR DIMMApplicationsJESD82JULY 2000JEDEC SOLID STATE TECHNOLOGY ASSOCIATIONNOTICEJEDEC standards and publications contain material that has been prepared, reviewed, andapproved through the JEDEC Board of Directors level and subsequent

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10、r call (703) 907-7559JEDEC Standard No. 82Page 1DEFINITION OF CDCV857 PLL CLOCK DRIVER FORREGISTERED DDR DIMM APPLICATIONS(Formerly JEDEC Council Ballot JCB-00-22, formulated under the cognizance of the JC-40 Committee on Digital Logic.)1 Background1.1 PurposeThe purpose is to provide a standard for

11、 a CDCV857 PLL clock device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. 1.2 ScopeThis standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of a CDCV857 PLL clo

12、ck device for registered DDR DIMM applications.2 Definitions for the purpose of this documentCI() Delta input capacitance.3 Device standard3.1 DescriptionThis PLL Clock Buffer is designed for 2.5 VDD and 2.5 AVDDoperation and differential data input and output levels. Package options include plastic

13、 Thin Shrink Small-Outline Package (TSSOP).The device is a zero delay buffer that distributes a differential clock input pair (CK, CK) to ten differential pair of clock outputs (Y0:9, Y0:9) and one differential pair feedback clock outputs (FBOUT, FBOUT). The clock outputs are controlled by the input

14、 clocks (CK, CK), the feedback clocks (FBIN, FBIN), the 2.5-V LVCMOS input (PWRDWN) and the Analog Power input (AVDD). When input PWRDWN is low while power is applied, the receivers are disabled, the PLL is turned off and the differential clock outputs are 3-stated. When AVDDis grounded, the PLL is

15、turned off and bypassed for test purposes.When the input frequency is less than approximately 20 MHz, which is below the operating frequency of the PLL, the device will enter a low power mode. An input frequency detection circuit on the differential inputs, independent from the input buffers, will d

16、etect the low frequency condition and perform the same low power features as when the PWRDWN input is low. When the input frequency increases to greater than approximately 20 MHz, the PLL will be turned back on, the inputs and outputs will be enabled and PLL will obtain phase lock between the feedba

17、ck clock pair (FBIN, FBIN) and the input clock pair (CK, CK).The PLL in the CDCV857 clock driver uses the input clocks (CK, CK) and the feedback clocks (FBIN, FBIN) to provide high-performance, low-skew, low-jitter output differential clocks (Y0:9, Y0:9). The CDCV857 is also able to track Spread Spe

18、ctrum Clocking (SSC) for reduced EMI.The CDCV857 is characterized for operation from 0 oC to 70 oC.JEDEC Standard No. 82Page 23.2 Pinout figureFigure 1 48-Pin dual inline package pinout3.3 Terminal functionsTable 1 Thermal functionsTerminalNameDescriptionElectricalCharacteristicsAGND Analog Ground G

19、roundAVDDAnalog power 2.5 V nominalCKClock input Differential inputCK Complementary clock input Differential inputFBIN Feedback clock input Differential inputFBIN Complementary feedback clock input Differential inputFBOUT Feedback clock output Differential inputFBOUT Complementary feedback clock out

20、put Differential inputPWRDWN Power down LVCMOS inputGND Ground GroundVDDQLogic and output power 2.5 V nominalY0:9 Clock outputs Differential outputsY0:9 Complementary clock outputs Differential outputsTOP VIEWVDDQ123456789101112131415161718192021222324484746454443424140393837353634333231302928272625

21、FBOUTGNDVDDQGNDGNDVDDQFBINFBINPWRDWNVDDQGNDGNDY9Y8Y8FBOUTY7Y7Y6Y6Y5Y5VDDQY9GNDGNDVDDQGNDY0Y0Y1Y1VDDQVDDQGNDCKCKY2Y2GNDY3Y3Y4Y4AGNDVDDQAVDDJEDEC Standard No. 82Page 33.4 Function table3.5 Logic diagramFigure 2 Logic diagram (positive logic)Table 2 Function tableInputs OutputsPLLAVDDPWRDWN CK CK YYFBO

22、UT FBOUTGND H L H L LH Bypassed/OffGND H H L HL L Bypassed/OffXLLHZZZZOfHLZZf2.5V(nom) H L H LHLHOn2.5V(nom) H H L H L H L On2.5V(no)X VDDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mAOutput clamp current, IOK(VOVDDQ) . . . . . . . . . . . . . . . . . . .

23、. . . . . . . . . . . . . . . . . . . 50 mAContinuous output current, IO(VO= 0 to VDDQ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mAContinuous current through each VDD, VDDQor GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mASt

24、orage temperature range, TSTG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 C to 150 CNOTES1. Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functiona

25、l operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the

26、input and output clamp-current ratings are observed.3. This value is limited to 3.6 V maximum.3.7 Recommended operating conditionsNOTES4. The PLL is turned off and bypassed for test purposes when AVDDis grounded. During this test mode, VDDQremains within the recommended operationing conditions and n

27、o timing parameters are guaranteed.5. VOXspecified at the DRAM clock input or the test load.6. VIDis the magnitude of the difference between the input level on CK and the input level on CK.7. VODis the magnitude of the difference of the output level between Yn and Yn, and FBOUT and FBOUT.Table 4 Rec

28、ommended operating conditions (see Note 4)Min Nom Max UnitVDDQOutput supply voltage2.32.5 2.7 VAVDDSupply voltage See Note 4VDDQVILLow-level input voltage PWRDWN 0.3 0.7 VVIHHigh-level input voltage PWRDWN 1.7 VDDQ+ 0.3 VVIInput voltage 0VDDQVIOHHigh-level output current 12 mAIOLLow-level output cur

29、rent 12 mAVIXInput differential-pair cross voltage(VDDQ/2) 0.2 (VDDQ/2) + 0.2VVOXOutput differential-pair cross- voltageSee Note 5 (VDDQ/2) 0.2 (VDDQ/2) + 0.2 VVINInput voltage level 0.3VDDQ+ 0.3VVIDInput differential voltage See Note 6 0.36VDDQ+ 0.6VVODOutput differential voltage See Note 7 0.70 VD

30、DQ+ 0.6 VTAOperating free-air temperature 0 70 CJEDEC Standard No. 82Page 53.8 DC specificationsTable 5 Electrical characteristics over recommended operating free-air temperature rangePARAMETER TEST CONDITIONSAVDD, VDDQMIN TYP MAX UNITVIKAll inputs II= 18 mA2.3 V 1.2 VVOHHigh output voltageIOH= 100

31、A2.3 to 2.7 VVDDQ0.1VIOH= 12 mA 2.3 V 1.7VOLLow output voltageIOL= 100 A2.3 to 2.7 V 0.1VIOL= 12 mA2.3 V 0.6IICK, FBINVI= VDDor GND2.7 V 10APWRDWN VI= VDDor GND 2.7 V 10IDDQDynamic supply currentCK and CK = 170 MHz2.7 V200 300 mAStatic supply currentCK and CK 20 MHz or PWRDWN = Low100 AIADDDynamic s

32、upply currentCK and CK = 170 MHz2.7 V912mAStatic supply currentCK and CK 20 MHz or PWRDWN = Low 100 ACICK and CKVI= VDDor GND2.5 V2.5 3.5pFFBIN and FBINVI= VDDor GND2.5 3.5CI()CK and CK VI= VDDor GND 0.25 0.25FBIN and FBINVI= VDDor GND0.25 0.25JEDEC Standard No. 82Page 63.9 Timing requirementsNOTES8

33、. The PLL must be able to handle spread spectrum induced skew.9. Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not required to meet the other timing parameters. (Used for low speed system debug.)10. Application clock frequency indicates a ran

34、ge over which the PLL must meet all timing parameters.11. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal after power up. During normal operation, the stabilization time is also the time required for the integ

35、rated PLL circuit to obtain phase lock of its feedback signal to its reference signal when the input clock frequency falls below 20 MHz, entered the power-down mode and later increased above 20 MHz.3.10 AC specificationsNOTES12. Static Phase Offset does not include Jitter.13. Period Jitter and Half-

36、Period Jitter specifications are separate specifications that must be met independently of each other.14. The Output Slew Rate is determined from the IBIS model into the load shown in Figure 3.15. The SSC requirements meet the Intel PC100 SDRAM Registered DIMM specification.16. Each Individual vendo

37、r must supply a plot (Gain vs. Frequency) of the PLLs closed loop bandwidth.Table 6 Timing requirements over recommended operating free-air temperature rangeAVDD, VDD= 2.5 V 0.2 VUNITMIN MAXfCKOperating clock frequency (see Notes 8 and 9) 60 170 MHzApplication clock frequency (see Notes 8 and 10) 95

38、 170 MHztDCInput clock duty cycle 40 60 %tSTABStabilization time (see Note 11) 100 secTable 7 Switching characteristics over recommended operating free-air temperature range(unless otherwise noted) (see Figures 3 and 4)PARAMETER DESCRIPTION DiagramAVDD, VDD= 2.5 V 0.2 VUNITMIN Nom MAXtjit(cc) Cycle-

39、to-cycle jitter see Figure 5 75 75 pst() Static phase offset (see Note 12) see Figure 6 50 0 50 pstsk(o) Output clock skew see Figure 7 100 pstjit(per) Period jitter (see Note 13) see Figure 8 75 75 pstjit(hper) Half-period jitter (see Note 13) see Figure 9 100 100 pstsl(i) Input clock slew rate see

40、 Figure 10 1.0 4.0 V/nstsl(o) Output clock slew rate (see Note 14) see Figure 10 1.0 2.0 V/nsThe PLL on the CDCV857 must be capable of meeting all the above test parameters while supporting SSC synthesizers (see Note 15) with the following parameters: SSC modulation frequency 30.00 50.00 KHzSSC cloc

41、k input frequency deviation 0.00 0.50 %CDCV857 PLL designs should target the values below to meet the 200 ps maximum of SSC induced skew:PLL loop bandwidth (see Note 16) 2.0 MHzPhase angle 0.031 degreesJEDEC Standard No. 82Page 74 Output Buffer Characteristics4.1 PurposeThe following table describes

42、 output-buffer Voltage vs. Current (V/I) characteristics that are sufficient to meet the requirements of registered DDR DIMM performance and timings. These characteristics are not necessarily production tested but can be guaranteed by design or characterization. Compliance with these curves is not m

43、andatory if it can be adequately demonstrated that alternate characteristics meet the requirements of the registered DDR DIMM application.Table 8 Output buffer voltage vs. current (V/I) characteristicsVoltage(V)Pull-Down Pull-UpI(mA) I(mA) I(mA) I(mA) I(mA) I(mA)TYP MIN MAX TYP MIN MAX2.7 91.7 79.2

44、112 127 100 1692.6 88.2 76.2 108 122 96.6 1622.5 84.8 73.2 104 117 92.8 1562.4 81.3 70.2 99.4 112 88.9 1502.3 77.9 67.2 95.3 108 85.1 1432.2 74.4 64.1 91.1 103 81.3 1372.1 71.0 61.1 86.9 98.2 77.4 1312.0 67.5 58.1 82.7 93.5 73.6 1241.9 64.1 55.1 78.6 88.7 69.8 1181.8 60.6 52.1 74.4 83.9 65.9 1121.7

45、57.2 49.0 70.2 79.2 62.1 1061.6 53.8 46.0 66.1 74.4 58.2 99.21.5 50.3 43.0 61.9 69.7 54.4 92.91.4 46.9 40.0 57.7 64.9 50.6 86.61.3 43.4 37.0 53.6 60.1 46.7 80.31.2 40.0 33.9 49.4 55.4 42.9 74.01.1 36.5 30.9 45.2 50.6 39.1 67.71.0 33.1 27.9 41.0 45.9 35.2 61.40.9 29.6 24.9 36.9 41.1 31.4 55.10.8 26.2

46、 21.9 32.7 36.3 27.6 48.80.7 22.8 18.9 28.5 31.6 23.8 42.50.6 19.4 16.0 24.4 26.8 19.7 36.20.5 15.7 12.5 20.1 22.1 16.2 29.90.4 12.5 9.9 16.1 17.5 12.7 23.80.3 9.4 7.4 12.1 12.9 9.4 17.70.2 6.3 4.9 8.1 8.5 6.1 11.70.1 3.1 2.5 4.0 4.2 3.0 5.800000000.1 3.1 2.4 4.0 4.0 2.8 5.60.2 6.2 4.8 8.0 7.8 5.4 1

47、0.90.3 9.2 7.2 11.9 11.3 7.9 16.00.4 12.2 9.5 15.8 14.7 10.2 20.8JEDEC Standard No. 82Page 80.5 15.1 11.8 19.6 17.8 12.3 25.30.6 17.9 14.0 23.3 20.7 14.2 29.50.7 20.7 16.1 27.0 23.4 15.9 33.50.8 23.4 18.2 30.5 25.8 17.4 37.10.9 26.1 20.2 34.0 28.0 18.8 40.51.0 28.7 22.1 37.4 29.9 19.9 43.61.1 31.2 2

48、4.0 40.8 31.6 20.8 46.41.2 33.6 25.7 44.0 33.1 21.6 48.91.3 35.9 27.4 47.1 34.3 22.1 51.11.4 38.1 29.0 50.1 35.3 22.6 53.01.5 40.2 30.4 53.0 36.1 22.9 54.61.6 42.2 31.8 55.7 36.7 23.1 55.91.7 44.0 32.9 58.3 37.3 23.3 57.11.8 45.7 34.0 60.8 37.7 23.5 58.01.9 47.2 34.8 63.0 38.1 23.7 58.82.0 48.6 35.5

49、 65.0 38.5 23.9 59.62.1 49.6 36.0 66.7 38.9 24.1 60.22.2 50.5 36.4 68.1 39.2 24.2 60.82.3 51.1 36.7 69.1 39.5 24.3 61.32.4 51.6 37.0 69.8 39.7 24.5 61.82.5 52.0 37.2 70.4 40.0 24.6 62.32.6 52.3 37.4 70.8 40.3 24.7 62.72.7 52.6 37.6 71.1 40.5 24.9 63.12.8 52.8 37.8 71.4 40.7 25.0 63.52.9 53.0 38.0 71.7 40.9 25.1 63.93.