1、JEDEC SOLID STATE TECHNOLOGY ASSOCIATIONJESD82-22NOVEMBER 2006JEDECSTANDARDInstrumentation Chip Data Sheet forFBDIMM Diagnostic SenselinesNOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approvedthrough the JEDEC Council level and subsequently reviewed a
2、nd approved by the EIA GeneralCounsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability andimprovement of products, and assisting the purchaser in selecting and obtai
3、ning with minimum delaythe proper product for use by those other than JEDEC members, whether the standard is to be usedeither domestically or internationally. JEDEC standards and publications are adopted without regard to whether or not their adoption mayinvolve patents or articles, materials, or pr
4、ocesses. By such action JEDEC does not assume anyliability to any patent owner, nor does it assume any obligation whatever to parties adopting theJEDEC standards or publications. The information included in JEDEC standards and publications represents a sound approach to product specification and app
5、lication, principally from the solid state device manufacturer viewpoint. No claims to be in conformance with this standard may be made unless all requirements stated in thestandard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publicationshould be a
6、ddressed to JEDEC Solid State Technology Association, 2500 Wilson Boulevard,Arlington, VA 22201-3834, (703)907-7559 or www.jedec.org. Published by JEDEC Solid State Technology Association 2006 2500 Wilson Boulevard Arlington, VA 22201-3834 This document may be downloaded free of charge, however JEDE
7、C retains the copyright on this material. By downloading this file the individual agrees not to charge for or resell the resulting material. Price: Please refer to the current Catalog of JEDEC Engineering Standards and Publications at www.jedec.org Printed in the U.S.A. All rights reserved PLEASE! D
8、ONT VIOLATE THE LAW! This document is copyrighted by the JEDEC Solid State Technology Association and may not be reproduced without permission. Organizations may obtain permission to reproduce a limited number of copies through entering into a license agreement. For information, contact: JEDEC Solid
9、 State Technology Association 2500 Wilson Boulevard Arlington, Virginia 22201-3834 or call (703) 907-7559 JEDEC Standard No. 82-22Page 1INSTRUMENTATION CHIP DATA SHEET FOR FBDIMM DIAGNOSTIC SENSELINES(From JEDEC Board Ballot JCB-06-53, formulated under the cognizance of the JC-40.1 Subcommittee on C
10、MOS/BiCMOS Digital Logic.)1 ScopeThis device is a one-chip spectrum analyzer that operates in the frequency range from 1 to 2 GHz.It requires no external components except some filtering of the voltage supply (one inductor, one bypasscapacitor).The frequency of the VCO is adjusted by an internal DAC
11、. No PLL loop is used to lock the VCO to areference frequency. A counter is used to determine the VCO frequency.The device has a serial I2C data interface. The device is available in a 28 pin TQFN package and is specified over the extended industrial (-40 C to +85 C) temperature range.2 Features Inp
12、ut Frequency Range 1 2 GHz Integrated Frequency Counter 50 dB Dynamic Range 3.3 V power supply Low Power Low Cost Small 28 pin TQFN Packages Integrated I2C serial interfaceJEDEC Standard No. 82-22Page 22.1 Temperature Range / PackageFunctional Diagram / Pin Configuration2.2 DC electrical characteris
13、tics456317161918GNDVddRF_IN4RF_IN3RF_IN2RF_IN1SCLSDADACADCI2CLogAmp27 26 25 124121289 10 11 11282RF_IN5RF_IN6RF_IN8RF_IN10RF_IN11RF_IN9RF_IN16RF_IN15RF_IN14RF_IN13GNDGND1312320 GNDRF_IN12GNDGND22147RF_IN7 15 GNDGNDGND1000 Divider 16bit CounterPARAMETER CONDITIONS MIN TYP MAX UNITSSupply Voltage 2.97
14、 3.3 3.63 VJEDEC Standard No. 82-22Page 32.3 AC electrical characteristics2.4 I2C electrical characteristicsPARAMETER CONDITIONS MIN TYP MAX UNITSI2C Clock Frequency 400 kHzLocal Oscillator No. 1 Range 1000 1600 MHzLocal Oscillator No. 2 Range 1600 2000 MHzLocal Oscillators Step Size 4MDetected Pow
15、er Range -80 -30 dBmInput Frequency Range 1000 2000 MHzIF Detection Bandw idth 10 MHzInput to Input Isolation 2 GHz 20 30 dBLocal Oscillator Drif t over time 500 kHz/secLocal Oscillator Frequency Change due to Changes on the Supply Voltage200mV voltage step on supply 5MVLocal Oscillator Drift over t
16、emperature 0.1 MHz/degPow er Reading Response Timemeasured from time of programming the DA C 100 sReceiver Gain Flatness w ithin f +/- 10MHz +/- 0.5 dBReceiver Selectivity at f 20MHz 5 dBReceiver Selectivity at f 40MHz 10 dBReceiver Selectivity at f 100MHz 25 dBPARAM ETER CONDITIONS M IN TYP M AX UN
17、ITSClock Speed 400 KHzInput Logic Level High 0.7 x Vcc VInput Logic Level Low 0.3 x Vcc VInput Hysteresis 0.05 x Vcc VInput Leakage Current Digital Inputs 0 or Vcc 0.1 1 AInput Capacitance 610pFOutput Logic Level Low 0.6 VOutput Logic Level Low Isink = 3mA 0.4 VThree-State Leakage Current Digital In
18、puts 0 or Vcc -10 +10 AThree-State Output Capacitance 610pFI2C Digital Output - SDAI2C Digital Input - SCL, SDAJEDEC Standard No. 82-22Page 43 Digital Interface DescriptionBasic FunctionThe device features an I2C Bus compatible 2-wire interface consisting of a serial data line (SDA) and a serial clo
19、ckline (SCL). The device is a transmit/receive slave-only device, relying upon a master to generate a clock signal. Themaster initiates data transfer on the bus and generates SCL to permit that transfer. A master communicates to thedevice by transmitting the proper address followed by command and/or
20、 data words. Each transmit sequence is framedby a START (S) and STOP condition (P). Each word transmitted over the bus is 8 bits long and is always followed byan acknowledge clock pulse. The device contains drives that re open-drain, requiring a pullup resistor (500 or greater)to generate a logic hi
21、gh voltage. Bit TransferOne data bit is transferred during each SCL clock cycle. The data on SDA must remain stable during the high periodof the SCL clock pulse. Changes in SDA while SCL is high are control signals (see START and STOP Conditions).SDA and SCL idle high when the I2C bus is not busy.St
22、art and Stop ConditionsWhen the serial interface is inactive, SDA and SCL idle high. A master device initiates communication by issuing aSTART condition. A START condition is a high-to-low transition on SDA with SCL high. A STOP condition is alow-to-high transition on SDA while SCL is high. Repeated
23、 Start ConditionsA repeated Start (Sr) condition is a Start condition that occurs when another Start conditions has occurred earlier butno Stop condition occurred in the meantime. A repeated Start may indicate a change of data direction on the bus.Acknowledge Bit (ACK)The acknowledge bit (ACK) is th
24、e ninth bit attached to any 8-bit data word. ACK is always generated by thereceiving device. Write Data FormatIn write mode (R/W = 0), data that follows the address byte controls the device.Read Data FormatIn read mode (R/W = 1), the device writes data to the bus.I2C AddressesThe four MSBs of the ch
25、ip address are hard-coded (b4 to b7) whereas the three LSBs will be sensed by the Chip asthe DC that has been applied to PINs 1 (A0), 2 (A1), and 3 (A2). Therefore, on a single I2C bus, up to eight spectrumanalyzers can be used.JEDEC Standard No. 82-22Page 5Table 1 - Device AddressTable 2 - Command
26、Byte Definitions Figure 1 - Data SequencePin DescriptionPin DescriptionV(RF_IN1) V(RF_IN2) V(RF_IN3) Device Address (A6A0)GND GND GND 0101 000Vcc GND GND 0101 001GND Vcc GND 0101 010Vcc Vcc GND 0101 011GND GND Vcc 0101 100Vcc GND Vcc 0101 101GND Vcc Vcc 0101 110Vcc Vcc Vcc 0101 111D6 D5 D4 D3 D2 D1
27、D00 0 0 MUX3 MUX2 MUX1 MUX0Four bit data for selecting one out of 16 RF inputs (multiplexer)0 0 1 X DAC9 DAC8 DAC7Control word to load the DAC data including the three MSBs. The remaining 7 bits are transmitted in the following byte.010XXXXControl word to start uploading the ADC data to the master (
28、1 Byte)011XXXXControl word to start uploading the Counter Registers to the master (2 Bytes)SERIAL DATA INPUTFunctionA0A1A2A3A4A5A6SR/ W =0D0D1D2D3D4D5D6D7A0A1A2A3A4A5A6SrPR/ W =1ACK ACKACK ACKACKMSB LSBD8D9D10D11D12D13D14D15D0D1D2D3D4D5D6D7JEDEC Standard No. 82-22Page 64 Pin DescriptionTable 3 - Pin
29、 Description4.1 Detailed DescriptionThe device is a one-chip spectrum analyzer. It is designed to find test signals within a spectrum ofinterferers and determine the power of these test signals. It uses a mixer to mix the receive signal to an IFof 10 MHz and use a logarithmic amplifier to determine
30、the power of this signal. The local oscillator that isused for the mixing is a free-running VCO that is controlled by a DAC. The DAC can be stepped throughits output voltage range to sweep the VCO over a frequency range that goes from 1000 to 2000 MHz. Dueto the fact, that no image rejection is impl
31、emented, the receiver receives signals within a bandwidth that isdouble the cut-off frequency of the low pass filter. This is due to the simple architecture and has to be takeninto account in case blocking signals exist at the RF inputs that are not separated from the wanted receivesignals by more t
32、han this bandwidth. Due to the fact that the VCO is free-running and not locked to a PLL,its frequency is not stable and will change over time with temperature and also due to switching inside thechip or with changes on the supply voltage. However, the changes will be limited to a numbercorrespondin
33、g to a few codes of the DAC, so that by scanning the adjacent DAC codes, the signal can befound easily. One possible application is the assessment of the quality of interconnects in digital computer hardware, if this hardware is able to transmit a test signal that contains at least one harmonic that
34、 falls into the frequency range of this spectrum analyzer. By coupling a part of this signal from different locations within the signal path and determining the power of these signals, the quality of the interconnect can be determined either based on the absolute power reading or relative to results
35、 from previous measurements.PIN NAME FUNCTION1 RF_IN1 RF Input, also A0 bit of chip address2 RF_IN2 RF Input, also A1 bit of chip address3 RF_IN3 RF Input, also A2 bit of chip address4, 5, 6, 7, 8, 9, 10, 11, 12, 25, 26, 27, 28RF_Inx RF Input13, 14, 15, 16, 20, 21, 22, 23, 24GND Ground PIN17 SCL Ser
36、ial Port Clock18 SDA Serial Port Data19 Vdd Supply VoltageJEDEC Standard No. 82-22Page 74.1 Detailed Description (contd)Figure 2 - Basic PrincipleBy adding the capacitive taps to the signal path, the original point-to-point structure is transferred into apoint-to-multipoint architecture with one tra
37、nsmit node and N+1 receive nodes (Figure 3).Figure 3 - Point-to-Multipoint ArchitecturePROCESSOR MEMORYTransmitter ReceiverTest Signal 3.2 Gbit/sfFundamental 1.6GHzHarmonicsSpectrum AnalyzerInterconnectRF Sense LinePower Measurement ResultsCapacitive Coupling Capacitive CouplingPROCESSORTransmitter
38、ReceiverSpectrum AnalyzerJEDEC Standard No. 82-22Page 84.1 Detailed Description (contd)In case of differential signal lines, a special layout is necessary in order to prevent the signals from bothlines to cancel out on the sense lines (Figure 4). Figure 4 - Additional Capacitors4.2 Basic Scanning Al
39、gorithmSince there is no reference frequency available to the spectrum analyzer, the frequency of the oscillator isnot exactly known. Therefore, at the beginning of a measurement, the whole DAC range is used to sweepthe oscillator from its minimum to its maximum frequency. As long as the test signal
40、 frequency lies withinthis range, at least one DAC code can be found that yields the maximum power reading. In case of only thetest signal is present and no interferers, there will be only one detectable maximum. In case of interferers,this algorithm will result in more than one DAC code with a powe
41、r reading considerably higher than thenoise level. In this case, a software algorithm can be used to switch off the test signal so that the powerreading for this signal will change whereas the power reading for interferers will not change. This DACsetting can then be held constant in order to measur
42、e the power of the test signal on all available sense lineinputs. As long as the oscillator frequency remains within a window as defined by the receive bandwidth ofthe spectrum analyzer, there is no need for re-calibration.4.3 Detect Interconnect ProblemsIn case of interconnect problems i.e., broken
43、 connections or connections that have become resistive, the signal level on the data lines will change. This change can be detected with the spectrum analyzer. In case of memory modules, the level of the test signal on the motherboard as well as on the memory module can be compared and in case of me
44、mory errors it can be easily distinguished between interconnect faults and memory hardware errors.-PROCESSORTransmitter ReceiverSpectrum Analyzer+2C CC 2CJEDEC Standard No. 82-22Page 9Figure 5 - Typical Application Circuit456317161918DACADCI2CLogAmp27 26 25 124121289 10 11 11282RF_IN5RF_IN6RF_IN8RF_
45、IN10RF_IN11RF_IN9RF_IN16RF_IN15RF_IN14RF_IN131312320RF_IN1222147RF_IN7 15RF_IN1A1RF_IN2RF_IN3RF_IN4A2 A0SCLSDAVccI2C Connection1000 Divider 16bit CounterJEDEC Standard No. 82-22Page 10JEDEC Standard No. 82-22Page 11JEDEC Standard No. 82-22Page 12NOTICE JEDEC standards and publications contain materi
46、al that has been prepared, reviewed, and approved through the JEDEC Board of Directors level and subsequently reviewed and approved by the JEDEC legal counsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and p
47、urchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. JEDEC standards a
48、nd publications are adopted without regard to whether or not their adoption may involve patents or articles, materials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or publicat
49、ions. The information included in JEDEC standards and publications represents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may be further processed and ultimately become an ANSI/EIA standard. No claims to be in conformance with this standard may be made unless all requirements stated in the standardare met. Inquiries, comments, and suggestions relative to the content of this JEDEC
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