1、JEDEC SOLID STATE TECHNOLOGY ASSOCIATIONJESD82-27MAY 2007JEDECSTANDARDDefinition of the SSTUB32869 RegisteredApplications Buffer with Parity for DDR2 RDIMM NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors lev
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9、thout permission. Organizations may obtain permission to reproduce a limited number of copies through entering into a license agreement. For information, contact: JEDEC Solid State Technology Association 2500 Wilson Boulevard Arlington, Virginia 22201-3834 or call (703) 907-7559 JEDEC Standard No. 8
10、2-27Page 1DEFINITION OF THE SSTUB32869 REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS(From JEDEC Board Ballot JCB-07-43, formulated under the cognizance of the JC-40 Committee on Digital Logic.)1 ScopeThis standard defines standard specifications of DC interface parameters, switching para
11、meters, and test loading for definition of the SSTUB32869 registered buffer with parity for driving heavy load on high-density DDR2 RDIMM applications. A typical application would be a 36 SDRAM planar DIMM.The SSTUB32869 is identical in functionality to the SSTU32S869, SSTU32D869 SSTUA32S869, and SS
12、TUA32D869 devices respectively but specify tighter timing characteristics and a higher application frequency of up to 410MHz. The purpose is to provide a standard for the SSTUB32869 (see Note) logic devices, for uniformity, multiplicity of sources, elimination of confusion, ease of device specificat
13、ion, and ease of use.NOTE The designations SSTUB32869 refers to the part designation of a series of commercial logic parts common in the industry. This number is normally preceded by a series of manufacturer specific characters to make up a complete part designation.2 Device standard2.1 DescriptionT
14、his 14-bit 1:2 registered buffer with parity is designed for 1.7 V to 1.9 V VDDoperation.All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8 V CMOS drivers optimized to drive the DDR2 DIMM load, following the SSTL_18 standa
15、rd. They provide 50% more dynamic driver strength than the standard SSTUB32866 outputs. The SSTUB32869 operate from a differential clock (CK and CK). Data are registered at the crossing of CK going high, and CK going low.The device supports low-power standby operation. When the reset input (RESET) i
16、s low, the differential input receivers are disabled, and un-driven (floating) data, clock and reference voltage (VREF) inputs are allowed. In addition, when RESET is low all registers are reset, and all outputs except PTYERR are forced low. The LVCMOS RESET input must always be held at a valid logi
17、c high or low level.To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power up.In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with respect to CK and CK. Therefore, no timing relationship ca
18、n be guaranteed between the two. When entering reset, the register will be cleared and the outputs will be driven low quickly, relative to the time to disable the differential input receivers. However, when coming out of reset, the register will become active quickly, relative to the time to enable
19、the differential input receivers. JEDEC Standard No. 82-27Page 22 Device standard (contd)2.1 Description (contd)SSTUB32869 must ensure that the outputs remain low as long as the data inputs are low, the clock is stable during the time from the low-to-high transition of RESET and the input receivers
20、are fully enabled. This will ensures that there are no glitches on the output.If the data inputs are not held low, then DCS and CSR must be held high, DODT and DCKE must be held low, and all other inputs must remain stable (either low or high) for a minimum of tACT(max) after the rising edge of RESE
21、T. The device monitors both DCS and CSR inputs and will gate the Qn, PPO (Partial-Parity-Out) and PTYERR1 (Parity Error) Parity outputs from changing states when both DCS and CSR are high. If either DCS or CSR input is low, the Qn, PPO and PTYERR outputs will function normally. The RESET input has p
22、riority over the DCS and CSR controls and will force the Qn and PPO outputs low and the PTYERR1 high. The SSTUB32869 include a parity checking function. The SSTUB32869 accept a parity bit from the memory controller at its input pin PARIN one or two cycles after the corresponding data input, compares
23、 it with the data received on the D-inputs and indicates on its open-drain PTYERR1 pin (active low) whether a parity error has occurred. The number of cycles depends on the setting of C1, see Figure 6 and 7.When used as a single device, the C1 inputs are tied low. When used in pairs, the C1 inputs a
24、re tied low for the first register (front) and the C1 inputs are tied high for the second register. When used as a single register, the PPO and PTYERR1 signals are produced two clock cycles after the corresponding data input. When used in pairs, the PTYERR1 signals of the first register are left flo
25、ating. The PPO outputs of the first register are cascaded to the PARIN signals on the second register (back). The PPO and PTYERR1 signals of the second register are produced three clock cycles after the corresponding data input. Parity implementation and device wiring for single and dual die is desc
26、ribed in Figure 1.If an error occurs, and the PTYERR1 is driven low, it stays low for two clock cycles or until RESET is driven low. For the case where a parity error occurs just before the device enters the low-power mode (LPM), see Table 4 on page 8, Figure 18, Figure 8 on page 13, and Figure 20.
27、The parity error output PTYERR1 will be reset to high by RESET transitioning low and will not be decoded until after RESET goes high and DCS and/or CSR are asserted low.The DIMM-dependent signals (DCKE, DCS, CSR and DODT) are not included in the parity check computations.Figure 1 .Parity implementat
28、ion and device wiring for SSTUB32869 PTYERR1 W1Register 1(Front)Parin1, W4NC, A8ParinPPO1, W8 Parin1, W4NC, A4Register 2(Back)NC, A8NC, A11Set C1 = 0 f or Register 1; Set C1 = 1 f or Register 2. NC denotes No ConnectJEDEC Standard No. 82-27Page 32 Device standard (contd)Package options include 150-b
29、all Thin Profile Fine Pitch BGA (TFBGA) (11 19 array, 8.0 13.0 mm body size, 0.65 mm pitch, 1.2mm height, MO-246, Variation TBD).2.2 150-ball TFBGA (MO-246xx)Figure 2 Pinout configuration1(TOP VIEW)23456789101ABCDEFGHJKLMNPRTUVWJEDEC Standard No. 82-27Page 42 Device standard (contd)2.3 Pinout top vi
30、ew for 150-ball TFBGA150-ball, 11 19 grid, TOP VIEWFigure 3 specifies the pinout for SSTUB32869. Unlike other configurable registers the device has symmetric pinout with center inputs and outputs to the left and right sides. Therefore the pinout for the device in front configuration is identical to
31、pinout in back configuration. The recommended placement is back to back on both sides of the PCB. VIAs for the inner ball connections (Vdd, GND, Inputs) are to be placed at the NB locations.NB indicates no ball is populated at that gridpoint. NC denotes a no-connect (ball present but not connected t
32、o the die).Figure 3 Pinout top view for 150-ball TFBGANote 1 MCL denotes input pin that must be connected Low. Register Vendors: Implement NC or input on Ball A3, A9, W3, W9 123456789101ANB VDDMCL(1)NC GND VREF GND NCMCL(1)VDD NCBVDD NB VDD GND GND GND GND GND VDD NB VDDCQCKEA VDD NB GND NB GND NB G
33、ND NB VDD QCKEBDQ2A VDD GND NB DCKE NB D2 NB GND VDD Q2BEQ3A VDD NB D3 NB NC NB DODT NB NC Q3BFQODTA VDD GND NB NC NB NC NB GND VDD QODTBGQ5A VDD GND D5 NB CLK NB D6 GND VDD Q5BHQ6A NB GND NB NC NB NC NB GND NB Q6BJQCSA VDD NB NC NB RESET NB CSR NB VDD QCSBKVDD VDD GND GND NB NB NB GND VDD VDD VDDLQ
34、8A VDD NB DCS NB CLK NB D8 NB VDD Q8BMQ9A NB GND NB NC NB NC NB GND NB Q9BNQ10A VDD GND D9 NB NC NB D10 GND VDD Q10BPQ11A VDD GND NB NC NB NC NB GND VDD Q11BRQ12A C1 NB D11 NB NC NB D12 NB VDD Q12BTQ13A VDD GND NB D13 NB D14 NB GND VDD Q13BUQ14A VDD NB GND NB GND NB GND NB VDD Q14BVVDD NB VDD GND GN
35、D GND GND GND VDD NB VDDWPTYERR1 VDDMCL(1)PARIN1 GND VREF GND PPO1MCL(1)VDD NBJEDEC Standard No. 82-27Page 52 Device standard (contd)2.4 Terminal functionsNOTE 1 Inputs D1, D4 and D7 and their corresponding outputs Qn are not included in this range. Table 1 Terminal functionsSignal Group Signal Name
36、 Type DescriptionUngated inputs DCKE, DODT SSTL_18 DRAM function pins not associated with Chip Select.Chip Select gated inputsD1 . D14(1)SSTL_18 DRAM inputs, re-driven only when Chip Select is LOW.Chip Select inputsDCS, CSR SSTL_18 DRAM Chip Select signals. These pins initiate DRAM address/command d
37、ecodes, and as such at least one will be low when a valid address/command is present. Re-driven outputsQ1A.Q14A, Q1B . Q14B, QCSA, QCSB QCKEA, QCKEB QODTA,QODTB1.8 V CMOS Outputs of the register, valid after the specified clock count and immediately following a rising edge of the clock.Parity input
38、PARIN1 SSTL_18 Input parity is received on pin PARIN1 and should maintain parity across the D1.D14(1)inputs, at the rising edge of the clock, one clock cycle after Chip Select is LOW.Parity outputPPO1SSTL_18Partial Parity Output. Indicates parity out of D1-D14(1)Parity error outputPTYERR1Open drain
39、When LOW, this output indicates that a parity error was identified associated with the address and/or command inputs. PTYERR will be active for two clock cycles, and delayed by in total 2 clock cycles for compatibility with final parity out timing on the industry-standard DDR2 register with parity (
40、in JEDEC definition).Configuration InputC1 1.8V LVCMOSWhen Low, register is configured as Register 1. When High, register is configured as Register 2. Clock inputs CK, CK SSTL_18 Differential master clock input pair to the register. The register operation is triggered by a rising edge on the positiv
41、e clock input (CK).Miscellaneous inputsRESET 1.8 V LVCMOSAsynchronous reset input. When LOW, it causes a reset of the internal latches, thereby forcing the outputs LOW. RESET also resets the PTYERR1 signal.VREF 0.9 V nominal Input reference voltage for the SSTL_18 inputs. Two pins (internally tied t
42、ogether) are used for increased reliability.VDD Power Input Power supply voltageGND Ground Input GroundJEDEC Standard No. 82-27Page 62 Device standard (contd)2.5 Function tableTable 2 Function table (each flip flop)Inputs OutputsRESET DCS CSR CK CKDn, DODT, DCKEQn QCSQODT, QCKEHLLLLLLHLLHHLHH L L L
43、or H L or H XQ0Q0Q0HLHLLLLHLHHHLHH L H L or H L or H XQ0Q0Q0HHLLLHLHHLHHHHH H L L or H L or H XQ0Q0Q0HHHLQ0HLHHHHQ0HHH H H L or H L or H XQ0Q0Q0LX or floatingX or floatingX or floatingX or floatingX or floatingLLLJEDEC Standard No. 82-27Page 72 Device standard (contd)2.5 Function table (contd)Table
44、3 Parity and standby function tableNOTE 1 Inputs D1, D4 and D7 are not included in this range.NOTE 2 PARIN1 arrives one (C1=0) or two (C1=1) clock cycles after data to which it applies.NOTE 3 This transition assumes PTYERR is high at the crossing of CK going high and CK going low. If PYTERR is low,
45、it stays latched low for two clock cycles or until RESET is driven low. PARIN1 is used to generate PPO1 and PTYERR1. Inputs OutputRESET DCS CSR CK CK of inputs = HD1.D14(1)PARIN1(2)PPO1(2)PTYERR1(3)HLX EvenLL HHLX OddLH LHLX EvenHH LHLX OddHL HHLL EvenLL HHLL OddLH LHLL EvenHH LHLL OddHL HHHHXXPPOn0
46、PTYERRn0HX X L or H L or H XXPPOn0PTYERRn0LX or floatingX or floatingX or floatingX or floatingX or floating X or floating L HJEDEC Standard No. 82-27Page 82 Device standard (contd)2.5 Function table (contd)Table 4 Parity error detect in low-power mode If a parity error occurs before the device ente
47、rs the low-power mode (LPM), the behavior of PPO1 and PTYERR1 is dependent on the mode of the device and the position of the parity error occurrence. This table illustrates the low-power-mode effect on parity detect. The low-power mode is activated on the n clock cycle when DCS and CSR go high. The
48、clock-edge position of a one-cycle data-input error relative to the clock-edge (n) which initiates LPM at the DCS and CSR inputs. If an error occurs, the PPO output may be driven high and the PTYERR1 output driven low. These columns show the clock duration for which the PPO signal will be held high
49、or the PTYERR1 signal will be held low. Not used.Input-Data Error Occurrence 1:2 Register-A Mode(C1=0)1:2 Register-B Mode(C1=1)PPO1Duration PTYERR1Duration PPO1Duration PTYERR1Duration n-21 Cycle 2 Cycles 1 Cycle 2 Cyclesn-11 Cycles afterLPM isde-asserted1 Cycles afterLPM isde-asserted2 Cycles afterLPM isde-asserted2 Cycles afterLPM isde-assertedn Not detected Not detected Not detected Not detectedJEDEC Standard No. 82-27Page 92 Device standard (contd)2.6 Logic diagramFigure 4 Logic d
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