JEDEC JESD82-30-2014 LRDIMM DDR3 Memory Buffer (MB) Version 1 0.pdf

1、JEDEC STANDARD LRDIMM DDR3 Memory Buffer (MB) Version 1.0 JESD82-30OCTOBER 2014 JEDEC SOLID STATE TECHNOLOGY ASSOCIATIONNOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors level and subsequently reviewed and app

2、roved by the JEDEC legal counsel.JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining

3、with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. JEDEC standards and publications are adopted without regard to whether or not their adoption may involve patents or articles, materials, or proc

4、esses. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or publications. The information included in JEDEC standards and publications represents a sound approach to product specification and app

5、lication, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may be further processed and ultimately become an ANSI standard. No claims to be in conformance with this standard may be made unless a

6、ll requirements stated in the standard are met.Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC at the address below, or refer to www.jedec.org under Standards and Documents for alternative contact information. Published

7、byJEDEC Solid State Technology Association 2014 3103 North 10th StreetSuite 240 South Arlington, VA 22201-2107 This document may be downloaded free of charge; however JEDEC retains the copyright on this material. By downloading this file the individual agrees not tocharge for or resell the resulting

8、 material. PRICE: Contact JEDEC PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by JEDEC and may not be reproduced without permission. For information, contact: JEDEC Solid State Technology Association 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 or refer to www.jedec.o

9、rg under Standards-Documents/Copyright Information. JEDEC Standard No. 82-30LRDIMM: Memory Buffer (MB), Version 1.0 Contents 1 Introduction .11.1 LRDIMM Memory Buffer Overview11.2 Memory Buffer Functionality .11.2.1 Memory Buffer Key Features.11.2.2 DDR SDRAM 11.2.3 Byte Group Signal Mapping 21.3 LR

10、DIMM DDR3 Memory Buffer Block Diagram 31.4 Interfaces 41.4.1 HOST Interface .41.4.2 DDR3 DRAM Interface41.4.3 SMBus Slave Interface41.5 References41.6 Glossary 52 Ballout and Package Information 72.1 588-Ball FBGA (20x38 Array, 25.2x13.5 mm Body Size, 0.65 mm Pitch, MO-301A Variation A) Pinconfigura

11、tion72.2 Pin Assignments for the LR-DIMM DDR3 Memory Buffer (MB)82.3 Package Information .163 Pin Descriptions 173.1 Pin Description 174 Host Interface Protocol and Requirement .214.1 MB Modes of operation .214.1.1 Direct Rank Addressing Mode 214.1.2 Rank Multiplication Mode 224.2 Command, Address,

12、and Control Signal usage 344.2.1 Command Signals.344.2.2 Address Signals 354.2.3 Control Signals364.3 Parity .394.3.1 Parity Timing Scheme Waveforms394.4 Dynamic 1T/3T Timing Transaction and Output Inversion Enabling/Disabling .414.5 Control Word Access Mechanism .454.6 Address Mirroring465 DRAM Int

13、erface Protocol and Requirement475.1 Signals and Usage 475.1.1 Command / Address .475.1.2 Control Signals485.1.3 Clock Outputs495.1.4 Reset.505.1.5 DRAM data bus.505.2 Turnaround Cycles506 Initialization .516.1 Initialization Overview .516.2 Power-on Initialization.526.2.1 Clock Stabilization Time t

14、STAB 536.3 Initialization with Stable Power (Soft Reset) .556.4 Host RCW to Configure MB566.5 Host MRS to Configure DRAM .566.6 Host to DRAM ZQ Calibration.576.7 MB-DRAM Training.576.8 Host-MB Training577 Electrical, Timing, Power and Thermal .597.1 Electrical DC and AC Parameters 597.1.1 Absolute m

15、aximum ratings .597.1.2 DC and AC Specifications 607.1.3 DC specifications, IDD Specifications.667.1.4 Input/Output Capacitance.677.2 AC and DC Input and Output Measurement Levels .687.2.1 Differential swing requirements for clock (CK - CK#) and strobe (DQS - DQS#) .687.2.2 Slew Rate Definitions for

16、 Differential Input Signals 69-i-JEDEC Standard No. 82-30LRDIMM: Memory Buffer (MB), Version 1.0 Contents (contd) 7.2.3 Single Ended AC and DC Output Levels 707.2.4 Differential AC and DC Output Levels 707.2.5 Single Ended Output Slew Rate .717.2.6 Differential Output Slew Rate .727.2.7 Reference Lo

17、ad for AC Timing and Output Slew Rate 737.2.8 Overshoot and Undershoot Specifications 747.3 Host Interface Electrical / Timing Specifications.767.3.1 CMD/ADDR/CTRL Input Bus Termination Requirement 767.3.2 DQ/DQS On-Die Termination (ODT) Requirement.777.3.3 DQ/DQS Output Driver DC Electrical Charact

18、eristics.787.3.4 Host Interface Input Timing and DQ/DQS Output Timing.797.4 DRAM Interface Electrical / Timing Specifications837.4.1 MDQ/MDQS On-Die Termination (MODT) Requirement 837.4.2 QCMD/QADDR/QCTRL/Yn_t/Yn_c DC and AC Output Parameters847.4.3 MDQ/MDQS DC and AC Output Parameters857.4.4 DRAM I

19、nterface Input and Output Timing .877.5 Data Setup, Hold and Slew Rate Derating967.6 Nominal and Tangent line slew rate measurement for Setup and Hold De-rating 987.7 Test circuits and switching waveforms for CMD/ADD/CNTRL/CK Inputs .1067.7.1 Parameter measurement information1067.7.2 Error output lo

20、ad circuit and voltage measurement information1098 Power Management 1118.1 CKE Power Management1118.1.1 2 DCKE mode (RDIMM Compatible Mode).1128.1.2 4 DCKE mode .1128.1.3 Soft CKE mode .1128.2 Memory Buffer Power Savings Modes1138.2.1 Memory Buffer CKE Power Down.1138.2.2 Clock Stopped Power Down Mo

21、de .1178.3 Dual Frequency Support .1209 Control Words .1219.1 Control Word Decoding.1219.2 Control Words Overview Map .1229.3 Function 0 Control Word Registers .1279.4 Function 1 Control Word Registers .1389.5 Function 2 Control Word Registers .1459.6 Function 3-11 Control Word Registers1529.7 Funct

22、ion 12 Control Registers.1579.8 Function 13 Control Registers.1589.9 Function 14 Control Word Registers .1609.10 Function 15 Control Word Registers .16110 MEMBIST16310.1 MEMBIST - Memory Built-In Self-Test 16310.2 MemBIST Feature Summary.16410.3 Function Overview 16610.3.1 Initialization MemBIST 166

23、10.3.2 Full Membist16610.4 Address Generation 16810.4.1 Address Definition .16810.4.2 Row addressing 16810.4.3 Column addressing .16810.4.4 Diagonal addressing (aka FastXY addressing).16910.4.5 Bank addressing .16910.4.6 Rank addressing .16910.4.7 Dynamic Address inversion.17010.5 Memory Data Format

24、ting 17110.5.1 Static Data Formats 17110.5.2 Dynamic Data Formats .17110.5.3 Circular shift register .17110.5.4 Random data generator 17210.6 Error Reporting and Control 17210.6.1 Failure Address Reporting 173-ii-JEDEC Standard No. 82-30 LRDIMM: Memory Buffer (MB), Version 1.0 Contents (contd) 10.6.

25、2 10.7 10.8 10.8.1 Multiple Failures 173 Per Address operations.174 Algorithmic Testing176 Initialization Tests176 10.8.2 10.9 Memory Stress Tests 176 Membist Flow Control FSM.177 10.10 Command State Finite State Machine 179 10.11 10.12 Timing parameters 181 Memory BIST Registers 18210.12.1 MBCSR: M

26、emBIST Control.18310.12.2 MB_START_ADDR: Memory Test Start Address 18610.12.3 MB_END_ADDR: Memory Test End Address.18610.12.4 MBFADDRPTR: Memory Test failure address pointer register.18710.12.5 MB_ERR_ADDR0: Memory Test Failure address 0 .19010.12.6 MB_ERR_ADDR1: Memory Test Failure address 1 .19110

27、.12.7 MB_ERR_ADDR2: Memory Test Failure address 2 .19110.12.8 MB_ERR_ADDR3: Memory Test Failure address 3 .19110.12.9 MB_ERR_ADDR4: Memory Test Failure address 4 .19210.12.10MB_ERR_ADDR5: Memory Test Failure address 5 .19210.12.11MB_ERR_ADDR6: Memory Test Failure address 6 .19210.12.12MB_ERR_ADDR7:

28、Memory Test Failure address 7 .19310.12.13MB_ERRDATA_BYTE0_1_0: Memory Test Error Data 1/019810.12.14MB_ERRDATA_BYTE1_1_0: Memory Test Error Data 1/019910.12.15MBLFSRSED: Memory Test Circular Shift and LFSR Seed .20711 Transparent Mode.20911.1 Transparent Mode.20911.1.1 Functions.20911.1.2 CA Signal

29、 mapping .21011.1.3 CA timing.21011.1.4 DQ Functionality and Timing.21111.1.5 Entry Procedure 21111.1.6 Exit Procedure.21111.1.7 Control Word .21211.1.8 Timing diagram .21312 LAI Mode.21512.1 LAI Mode Support (Optional) 21513 SMBus Interface and Temperature Sensor.21713.1 SMBus 2.0 Specification Com

30、patibility21713.2 Operating Range.21713.3 External Pins .21713.3.1 Serial Clock (SCL).21713.3.2 Serial Data (SDA)21713.3.3 Select Address (SA0, SA1, SA2) 21813.4 System Management Access21913.4.1 Slave Address .21913.4.2 Supported SMBus Commands22013.4.3 MB Register Access Protocols22013.5 SMBus Err

31、or Handling 22413.6 SMBus Resets 22413.6.1 SMBus Interface State Machine Reset .22413.6.2 SMBus transactions during reset 22413.7 Temperature Sensor (TS) .22413.7.1 EVENT_n Pin 22513.7.2 TS Register Address Map .22613.7.3 Capabilities Register .22713.7.4 Configuration Register 22913.7.5 Temperature

32、Registers .23114 Reset.23514.1 Introduction .23514.2 Platform Reset Functionality .23514.2.1 Platform RESET_n Requirements.23514.2.2 DDR3 LRDIMM Memory Buffer RESET_n Requirements 23514.2.3 Power-Up and Suspend-to-RAM Considerations236-iii-JEDEC Standard No. 82-30LRDIMM: Memory Buffer (MB), Version

33、1.0 Contents (contd) 14.3 Reset Types 23615 Configuration and Status Registers 23715.1 Access Mechanism .23715.1.1 Register Attribute Definition 23815.1.2 Number Notation .23915.1.3 Function Spaces .23915.2 Registers .24015.2.1 Register Map.24015.2.2 Register Description244Tables 1 DQ and DQS Mappin

34、g 22 MDQ and MDQS Mapping 23 588-Ball FBGA (20x38 Array, 13.5x25.2 mm Body Size, 0.65 mm Pitch, MO-301A Variation A)(Transparent, Top View) - Left Side .84 588-Ball FBGA (20x38 Array, 13.5x25.2 mm Body Size, 0.65 mm Pitch, MO-301A Variation A)(Transparent, Top View) - Right Side95 Memory Buffer Sign

35、als By Ball Number106 Memory Buffer Signal Types.177 Pin Description 178 Modes of operation for each DIMM type .219 Rank Multiplication Command Details.2210 RM bits for each DIMM type2311 Normal and Rank Multiplication Control Signal Connectivity without Rank 1 and Rank 5 Swap(F0RC2 DA4 = 1b) 2412 N

36、ormal and Rank Multiplication Control Signal Connectivity with Rank 1 and Rank 5 Swap(F0RC2 DA4 = 0b) . 2513 Normal (1:1), 2 Way (1:2) and 4 Way (1:4) Rank Multiplication Control Signal Decoding without Rank 1and Rank 5 Swap (F0RC2 DA4 = 1b).2614 Normal (1:1), 2 Way (1:2) and 4 Way (1:4) Rank Multip

37、lication Control Signal Decoding with Rank 1 and Rank 5 Swap (F0RC2 DA4 = 0b).2815 Precharge Single and Precharge All Command Control.3116 MRS Control3417 Command and MB Action .3518 CKE Modes .3719 Soft CKE command.3820 Address Mirroring4621 Command / Address signals .4722 Address Mirroring4823 Con

38、trol Signals4924 Data bus connections5025 MB Device Initialization Sequence5426 MB Device Initialization Sequence when Power and Clock are Stable.5627 Absolute maximum ratings over operating free-air temperature range.5928 Operating Conditions for the SMBUS interface.6029 AC Measurement Conditions f

39、or SMBUS interface.6030 Input Parameters for SMBUS interface.6031 DC Characteristics for SMBUS interface.6132 AC Characteristics for SMBUS interface.6333 Operating Electrical Characteristics 6534 DC Electrical characteristics6635 Capacitance values.6736 Differential AC and DC Input Levels .68-iv-JED

40、EC Standard No. 82-30LRDIMM: Memory Buffer (MB), Version 1.0 Contents (contd) 37 Differential Input Slew Rate Definition.6938 Single-ended AC and DC Output Levels.7039 Differential AC and DC Output Levels.7040 Single-ended Output Slew Rate Definition .7141 Differential Output Slew Rate Definition .7

41、242 AC overshoot/undershoot specification for Address, Command and Control pins7443 AC overshoot/undershoot specification for Clock, Data, and Strobe 7544 CMD/ADDR/CTRL Input Bus Termination 7645 DQ/DQS On-Die Termination7746 DQ/DQS Output Driver Impedance RON Requirement 7847 Host Interface Input T

42、iming Parameters7948 Host Interface DQ/DQS Output Timing Parameters8249 MDQ/MDQS On-Die Termination (MODT) for READ Operation.8350 QCMD/QADDR/QCTRL/Yn_t/Yn_c Ron and Output Slew Rate.8451 AC level for Slew Rate Measurement .8552 MDQ/MDQS Ron Requirement (for DRAM Interface WRITE Operation) .8653 DRA

43、M Interface MDQ/MDQS Input Timing Parameters .8754 Output timing requirements.8855 DRAM Interface Output Timing Parameters9056 MB Operating Spec for Different Physical Ranks9257 MB Operating Spec for Different Physical Ranks9258 Clock driver Characteristics at application frequency9559 Derating valu

44、es for DDR3-800/1066/1333/1600 tDS/tDH - (AC100) 9660 Derating values for DDR3L-800/1066/1333/1600 tDS/tDH - (AC90) 9761 CKE Management Control Register (in F0RC6) .11162 Soft CKE Command Definition11263 Control Word Decoding.12164 F0 Control Word Decoding12265 F1 Control Word Decoding12266 F2 Contr

45、ol Word Decoding12367 F3 Control Word Decoding12368 F3-10 RC10-11 Control Word Decoding .12469 F3-11 RC12-13 Control Word Decoding .12470 F4-11 RC0-9, 14-15 Control Word Decoding12471 F11 RC10-11 Control Word Decoding 12472 F12 Control Word Decoding12573 F13 Control Word Decoding12574 F14 Control Wo

46、rd Decoding12675 F15 Control Word Decoding12676 F0RC0: Global Features Control Word .12777 F0RC1: Clock Driver Enable Control Word.12778 F0RC2: Timing Control Word12879 F0RC3: Address/Command F3:10 = Rank0:7 respectively. F11 RC10 Reserved 155133 F3-10RC11: Write QODT Control Words; F3-10 = Rank0:7

47、respectively. F11RC11 Reserved .155134 F3-11 RC12: Reserved .156135 F3-11 RC13: Reserved .156136 F3 RC14-15: Reserved .157137 F4-11 RC0-6, 8-9, 14-15 input clock.10849 Qn and Yn Load circuit for propagation delay and slew measurement.10850 Voltage waveforms; propagation delay times10851 Voltage wave

48、forms address floating .10952 Calculating the virtual VTT crossing point.11053 Load circuit, ERROUT_n Outputs .11154 Power Down Mode Entry and Exit with IBT Off.11555 Power Down Mode Entry and Exit with IBT On.11756 Clock Stopped Power Down Entry and Exit with IBT On 11957 Clock Stopped Power Down E

49、ntry and Exit with IBT Off 12058 Errout_n Signal During DDR3 MB Training.13559 QCA Prelaunch, OCS_n, QODT, and QCKE Delay Features.14460 Errout_n Signal from MBIST to Normal Operation14861 Diagonal addressing examples .17262 Write Operation .17763 Read Operation.17764 Read, Modify .17765 MemBIST Flow Control State Machine .18166 Command State Machine18567 Transparent Mode Timing Diagram.21568 Maximum RL Value Versus Bus Capacitance (CBUS) for an SMBUS Bus21969 SMBUS WIRING DIAGRAM .22070 SMBus Configuration Read (Blo