JEDEC JESD82-31-2016 DDR4 Registering Clock Driver - DDR4RCD01.pdf

1、AUGUST 2016DDR4 Registering Clock Driver - JESD82-31JEDECSTANDARDJEDEC SOLID STATE TECHNOLOGY ASSOCIATIONDDR4RCD01 NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors level and subsequently reviewed and approved

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9、01-2107 or refer to www.jedec.org under Standards-Documents/Copyright Information. (This page is intentionally left blank)JEDEC Standard No. 82-31DDR4 REGISTERING CLOCK DRIVER - DDR4RCD01Contents-i-1 Scope.12 Device standard .22.1 Description .22.2 Features and Functions.22.2.1 Direct CS Modes 32.2.

10、2 Quad CS Modes 32.3 Initialization .52.3.1 Reset Initialization with Stable Power 72.4 Parity 82.4.1 Parity Timing Scheme Waveforms .92.5 Data Buffer Control Bus 122.5.1 Control Bus Signals 122.5.2 Control Bus Timing 122.5.3 Control Bus Commands 132.5.4 Command Sequences 132.5.5 Command Sequence De

11、scriptions 142.6 DQ Bus Termination in LRDIMM application232.7 Power saving modes.262.7.1 Register CKE Power Down 262.7.2 Clock Stopped Power Down Mode.322.8 Dual Frequency Support 352.8.1 Input Clock Frequency Change.352.9 Output Inversion Enabling/Disabling 372.9.1 1T Timing Only 412.10 ZQ Calibra

12、tion .412.11 Latency Equalization Support422.12 CA Bus Training Modes 422.13 Transparent Mode 442.14 Mechanical outline.452.15 Pinout .462.16 Terminal Functions Function tables 472.17 Logic diagram 522.18 Control Words532.18.1 Address Mirroring.532.18.2 Control Word Decoding542.18.3 RC00 - Global Fe

13、atures Control Word .552.18.4 RC01 - Clock Driver Enable Control Word 562.18.5 RC02 - Timing and IBT Control Word .562.18.6 RC03 - CA and CS Signals Driver Characteristics Control Word .562.18.7 RC04 - ODT and CKE Signals Driver Characteristics Control Word 572.18.8 RC05 - Clock Driver Characteristi

14、cs Control Word .572.18.9 RC06 - Command Space Control Word .572.18.10 RC08 - Input/Output Configuration Control Word 582.18.11 RC09 - Power Saving Settings Control Word .582.18.12 RC0A - RDIMM Operating Speed 592.18.13 RC0B - Operating Voltage VDD and VrefCA Source Control Word 592.18.14 RC0C - Tra

15、ining Control Word 602.18.15 RC0D - DIMM Configuration Control Word 602.18.16 RC0E - Parity Control Word 602.18.17 RC0F - Command Latency Adder Control Word.612.18.18 RC1x - Internal VREFCA Control Word 622.18.19 I2C Bus Control Words.63JEDEC Standard No. 82-31DDR4 REGISTERING CLOCK DRIVER - DDR4RCD

16、01Contents-ii-2.18.20 RC3x - Fine Granularity RDIMM Operating Speed.642.18.21 CW Selection Control Words .662.18.22 CW Data Control Word 672.18.23 IBT Control Word.672.18.24 ODT Input Buffer/IBT, QxODT Output Buffer and Timing Control Word 682.18.25 QxODT1:0 Write Pattern Control Word 692.18.26 QxOD

17、T1:0 Read Pattern Control Word.692.18.27 IBT and MRS Snoop Control Word .692.18.28 RCCx RCFFx - Error Log Register .703 I2C Bus Interface.713.1 Operating Range 713.2 External Pins 713.2.1 Serial Clock (SCL)713.2.2 Serial Data (SDA) .713.2.3 Select Address (SA0, SA1, SA2)723.3 System Management Acces

18、s733.3.1 Slave Address743.3.2 Supported I2C Bus Commands .743.3.3 Register Access Protocols.753.4 I2C Bus Error Handling803.5 I2C Resets.803.5.1 I2C Interface State Machine Reset803.5.2 I2C transactions during reset.804 Absolute maximum ratings 815 Input AC and DC Specifications825.1 CA Input Receiv

19、er Specifications.835.2 AC and DC Logic Input Levels for Differential Signals .885.2.1 Differential signal definition.885.2.2 Differential swing requirements for CK_t/CK_c885.2.3 Single-ended requirements for CK_t/CK_c895.3 Differential Input Cross point voltage .905.4 Differential Input Slew Rate D

20、efinitions for CK .925.5 Input buffer characteristics .925.6 CMOS Rail-to-Rail Input Levels for DRST_n 945.7 Overshoot and Undershoot Specifications 955.8 VrefCA Specifications .966 Output AC and DC Specifications 1036.1 Single-Ended Output Slew Rate 1036.2 Differential Output Slew Rate Definitions

21、for Yn_t / Yn_c and BCK_t / BCK_c.1046.3 Differential Output Cross Point Voltage1056.4 Register R-on and Weak Drive Specifications for Each Drive Strength 1066.5 ALERT_n Output Driver DC Electrical Characteristic .1096.6 Clock driver Characteristics.1097 DC specifications, IDD Specifications .1137.1

22、 DC Electrical Characteristics .1137.2 IDD Specification Parameters and Test Conditions 1138 Input/Output Capacitance 1179 Timing requirements 11910 I2C Electrical and Timing Specifications12111 Test circuits and switching waveforms .12511.1 Parameter measurement information .12511.2 Alert output lo

23、ad circuit and voltage measurement information .12711.3 DDR4 Register Reference Load 128JEDEC Standard No. 82-31DDR4 REGISTERING CLOCK DRIVER - DDR4RCD01Contents-iii-12 Recommended Filtering for the Analog Power supply (AVDD) 12913 Reference to other applicable JEDEC standards and publications .130T

24、able1: Revision History . iiTable2: DCS, DC - QxCS, QxC Mapping in Encoded QuadCS mode.3Table3: DDR4RCD01 Device Initialization Sequence.6Table4: DDR4RCD01 Device Initialization Sequence when Power and Clock are Stable8Table5: List of Signals for Data Buffer control 12Table6: Data Buffer Control Bus

25、 Command Table 13Table7: Multicycle Sequence for Write Commands.15Table8: Multicycle Sequence for Read Commands16Table9: Multicycle Sequence for MRS Write Commands .18Table10: Multicycle Sequence for BCW Write Commands.19Table11: Multicycle Sequence for BCW Read Commands21Table12: Default Write, Rea

26、d QxODT1:0 Signal High Time25Table13: Address Inversion 38Table14: Address Mirroring and Inversion.40Table15: Ball Assignment - 253-ball FCBGA, 15 x 20 Grid, TOP VIEW 46Table16: Terminal functions.47Table17: Direct DualCS mode Function table (CS mode setting 00) 49Table18: Direct QuadCS mode Functio

27、n table (CS mode setting 01) .49Table19: Encoded QuadCS mode Function table (CS mode setting 11) .50Table20: PLL function table .51Table21: Address Mirroring53Table22: Control Word Decoding.55Table23: RC00: Global Features Control Word .55Table24: RC01: Clock Driver Enable Control Word56Table25: RC0

28、2: Timing and IBT Control Word.56Table26: RC03: CA and CS Signals Driver Characteristics Control Word .56Table27: RC04: ODT and CKE Signals Driver Characteristics Control Word57Table28: RC05: Clock Driver Characteristics Control Word.57Table29: RC06: Command Space Control Word definition.57Table30:

29、RC08: Input/Output Configuration Control Word.58Table31: Parity Checking and DC2:0 input clock125Figure 66: Voltage and current waveforms; inputs active and inactive times 125Figure 67: Input Waveforms VIXrange measurement125Figure 68: Voltage waveforms; propagation delay times .126Figure 69: Voltag

30、e waveforms address floating .126Figure 70: Calculating the virtual Vcrossing point127Figure 71: Load circuit, ALERT_n Outputs .128Figure 72: Voltage waveforms, tALERT_HL Measurement.128Figure 73: Reference Load for AC Timing and Output Slew Rate 128Figure 74: AVDD Filtering.129JEDEC Standard No. 82

31、-31Page 1DDR4 REGISTERING CLOCK DRIVER - DDR4RCD011ScopeThis document defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the DDR4 Registering Clock Driver (RCD) with parity for driving address and control nets on DDR4 RDIMM and LRDIMM

32、 applications. Any TBDs as of this document, are under discussion by the formulating committee.The terms Registering Clock Driver, RCD, register or device are used interchangeably to refer to this device in the remainder of this specification.The purpose is to provide a standard for the DDR4RCD01 (s

33、ee Note) logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.NOTE The designation DDR4RCD01 refers to the part designation of a series of commercial logic parts common in the industry. This designation is normally preceded by

34、 a series of manufacturer specific characters to make up a complete part designation.JEDEC Standard No. 82-31Page 22 Device standard2.1 DescriptionThis 32-bit 1:2 registering clock driver with parity is designed for 1.2 V VDD operation.All inputs are pseudo-differential with an external or internal

35、voltage reference. All outputs are full swing CMOS drivers optimized to drive single terminated 2550 traces in DDR4 RDIMM and LRDIMM applications. The clock outputs Yn_t and Yn_c and control net outputs QxCKEn, QxCSn and QxODTn can be driven with a different strength to compensate for different DIMM

36、 net topologies. By disabling unused outputs the power consumption is reduced.The DDR4RCD01 operates from a differential clock (CK_t/CK_c). Inputs are registered at the crossing of CK_t going HIGH, and CK_c going LOW. The input signals could be either re-driven to the outputs or they could be used t

37、o access device internal control registers when certain input conditions are met. The control word mechanism is described in more detail in 2.18.2, Control Word Decoding. 2.2 Features and FunctionsThe DDR4RCD01 has three basic modes of operation associated with the DA1:0 bits in the DIMM Configurati

38、on Control Word (RC0D): In Direct DualCS mode (DA1:0 = 00) the component has two chip select inputs, DCS0_n and DCS1_n, and two copies of each chip select output, QACS0_n, QACS1_n, QBCS0_n and QBCS1_n. The inputs pins DC2:0 are forwarded to two sets of output pins, QAC2:0 and QBC2:0. This is the nor

39、mal operating mode (“QuadCS disabled” and “Encoded CS disabled”). In Direct QuadCS mode (DA1:0 = 01), the component has four chip select inputs, the two dedicated inputs DCS1:0_n and the DC0 input pin functioning as DCS2_n and the DC1 input pin functioning as DCS3_n, and two copies of each chip sele

40、ct output, QACS3:0_n and QBCS3:0_n. The input pin DC2 is forwarded to two output pins, QAC2 and QBC2. The output pins QAC1:0 and QBC1:0 are used as QACS3:2_n and QBCS3:2_n. This is the “QuadCS enabled” mode.In the two modes above the DDR4 register does not need to decode input signals to generate an

41、y chip select outputs. In Encoded QuadCS mode (DA1:0 = 11), two copies of four output chip selects, i.e., QACS3:0_n and QBCS3:0_n, are decoded out of two DCS1:0_n inputs and the DC0 input. The input pin DC2 is forwarded to two output pins, QAC2 and QBC2. The output pins QAC1:0 and QBC1:0 are used as

42、 QACS3:2_n and QBCS3:2_n. This is the “Encoded QuadCS” mode.When the DCS encoding is changed (i.e., when the setting in RC0D DA1:0 is updated), it is necessary for the host to precondition the signals driven on the pins which will be turned into chip select inputs with the correct voltage levels. Fo

43、r example, it is necessary to drive DCS3:2 both HIGH before RC0D DA1:0 is updated from 00 to 01. This is necessary to prevent a violation of the tMRDparameter.JEDEC Standard No. 82-31Page 32.2 Features and Functions (contd)Through the remainder of this specification, DCSn:0_n will indicate all of th

44、e chip select inputs, where n=1 for RCD0D DA0=0, and n=3 for RCD0D DA0=1. QxCSn:0_n will indicate all of the chip select outputs.2.2.1 Direct CS ModesCommands are sent to a single rank or multiple ranks, as determined by the DCSn:0_n and DCn:0 inputs. The number of input chip selects matches the num

45、ber of output chip selects in each of the two sets (A-outputs and B-outputs).The number of input chip selects is two (in Direct DualCS mode) or four (in Direct QuadCS mode).2.2.2 Quad CS ModesFor DIMMs using dual-die packages there is a need for four CS signals rather than the standard two. For thes

46、e modules two modes are available where four CS outputs are available. The memory controller can select by programming the CS mode control bits which of the two modes it wants to utilize.There are two ways of accomplishing this: by using four CS inputs from the host (DCS3:0_n). This is the Direct Qu

47、adCS mode. See 2.2.1, Direct CS Modes. by using two CS inputs and one of the chip ID inputs from the host (DCS1:0_n and DC0). See 2.2.2.1, Encoded QuadCS Mode.Table 1 Generic DCS - QxCS MappingInput CSOutput CSDirect DualCS mode Direct QuadCS mode Encoded QuadCS modeDCS0_n QxCS0_n QxCS0_n QxCS0_n, Q

48、xCS1_nDCS1_n QxCS1_n QxCS1_n QxCS2_n, QxCS3_nDCS2_n/DC0 n/a QxCS2_n n/aDCS3_n/DC1 n/a QxCS3_n n/aJEDEC Standard No. 82-31Page 42.2.2 Quad CS Modes (contd)2.2.2.1 Encoded QuadCS ModeWhen RC0D bit DA1 is set to 1 the DDR4 register decodes two sets of four QxCS_n outputs from two DCS_n inputs by using

49、the DC0 as the encoding input. No additional address bits are used.All commands including read, write, precharge, refresh and MRS commands are sent to the rank selected by the two chip selects and chip ID bit 0 coming from the host.The memory controller needs to handle commands in the same way it would handle a DIMM with two times as many chip selects.2.3 InitializationTo ensure defined outputs from the register before a stable clock has been supplied, the register mu