JEDEC JESD96A-2006 Radio Front End-Baseband (RF-BB) Interface《无线前段 基带接口》.pdf

1、 JEDEC STANDARD Radio Front End-Baseband (RF-BB) Interface JESD96A (Revision of JESD96, April 2004) FEBRUARY 2006 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors leve

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9、btain permission to reproduce a limited number of copies through entering into a license agreement. For information, contact: JEDEC Solid State Technology Association 2500 Wilson Boulevard Arlington, Virginia 22201-3834 or call (703) 907-7559 JEDEC Standard No. 96A -i- RADIO FRONT ENDBASEBAND (RF-BB

10、) INTERFACE CONTENTS Page Introduction . iii Foreword .iii 1 Scope 1 2 References2 2.1 Informative Specifications2 2.2 Normative Specifications2 3 Terminology 2 3.1 Terms and Definitions.2 3.2 Acronyms and Abbreviations4 3.3 Numeric Representation5 4. Electrical Layer.5 4.1 Electrical Layer Overview

11、 5 4.2 Power Supply Characteristics (Informative).7 4.3 Driver Cell DC Specifications 7 4.4 Driver Cell AC Specifications 8 4.5 Receiver Cell Specifications .12 4.6 Interconnect Specifications.13 4.7 Physical Layer I/O Timing Requirements.15 5 Link Layer.21 5.1 Link Service21 5.2 Initialization Stat

12、e Diagram 22 5.3 Clock-Data Synchronization (Deskew).29 5.4 Sync Mark.29 5.5 States of Operation29 5.6 Slower Speed, Shorter Distance and Lower Power.31 5.7 Extensibility31 6 Transport Layer32 6.1 Transport Service33 6.2 Initialization33 6.3 Header Field33 6.4 Streaming Data Field 34 6.5 Control Dat

13、a Field 35 6.6 Register Data Field (Configuration) .36 6.7 Parity (P) Field37 6.8 Frame Boundary and Null Field37 7 Registers.38 7.1 Register Overview 38 Annex A - Simulations.44 Annex B - Clock Frequency Choice .49 Annex C - Differences between JESD96A and JESD96 .52 JEDEC Standard No. 96A -ii- RAD

14、IO FRONT ENDBASEBAND (RF-BB) INTERFACE CONTENTS FIGURES Figure 1: JC-61 Interface Layer Diagram. 1 Figure 2: JC-61 Electrical Layer Connections 6 Figure 3: DC Output Reference System Load 8 Figure 4: AC Reference System Load 10 Figure 5: Driver AC Waveform Parameters . 10 Figure 6: Differential Outp

15、ut Skew 11 Figure 7: Receiver Reference Circuit . 12 Figure 8: Example Block Diagram of a FED to BED Link 15 Figure 9: Eye Diagram of data and clock at the receiver input. 16 Figure 10: Data and Clock Transition Dependent Skews. 17 Figure 11: Clock Duty Cycle Error. 18 Figure 12: JC-61 Link Layer an

16、d adjacent layers. 21 Figure 13: Link Layer initialization sequence 22 Figure 14: Power-off and RESET State 23 Figure 15: START_INIT State . 24 Figure 16: DESKEW STATES 25 Figure 17: LINK STATE 25 Figure 18: Clock and Data Pre-Alignment Requirements 29 Figure 19: Extensibility options 32 Figure 20:

17、General frame format 32 Figure 21: Frame Header 33 Figure 22: Streaming field example 34 Figure 23: Control access frame . 35 Figure 24: Register access frames 36 TABLES Table 1: Link Power Supply Characteristics 7 Table 2: Driver DC Specifications 8 Table 3: AC Reference System Load Characteristics

18、. 9 Table 4: AC Specifications. 11 Table 5: Receiver DC Specifications 12 Table 6: Receiver AC Specifications 13 Table 7: Suggested Corner Case Interconnect Specifications. 14 Table 8: Budgeted Interconnect Timing Errors 19 Table 9: Corner case Interconnect Channel Timing Errors 19 Table 10: Recomme

19、nded Link Timing Specifications . 20 Table 11: FED State Machine Transitions 27 Table 12: BED State Machine Transitions . 28 JEDEC Standard No. 96A -iii- RADIO FRONT END-BASEBAND (RF-BB) INTERFACE Foreword This standard establishes the requirements for an interface between Radio Front End (RF) and B

20、aseband (BB) integrated circuits (IC). These requirements are intended to ensure that multiple RF and baseband IC vendors can collaborate and design a common IC interface allowing each of the devices to work with each other. Included are requirements for electrical signaling, link layer state machin

21、es and register map definitions. Introduction This interface is a high-speed, low latency digital interface that has been defined primarily for wireless local area networking applications but can be used for other RF to BB links such as used in metro area networking and wide area networking applicat

22、ions. This interface allows the radio front end of a wireless network controller to be separated from the base-band and MAC device(s) by up to 50 cm. A typical example is to connect a radio front end in the upper (screen) portion of a laptop computer to a base-band device on the motherboard. Lower p

23、ower options are also defined for shorter distances. The basic interface consists of three differential signals totaling to six pins. A clock signal must be provided by the FED on one pair of pins along with two pairs of pins for data transfers from the FED to BED and in the reverse direction. A sep

24、arate pair is dedicated for either direction. Figure 1 illustrates the pin connections for the RF-BB interface. An optional pair of pins can be assigned for a return clock from the BED to the FED. The interface provides three, concurrent, logical channels for communication: a streaming data channel,

25、 a control channel and a register access channel. Each of these channels can be programmed by the BED, subject to the constraints indicated by the FED in its capability registers. The FED determines the clock frequency, while the BED can select the data frame formats subject to the constraints indic

26、ated by the FED in its capability registers . Registers defined in clause 7 control the streaming rate, data and control word sizes, and optional configurations. I.1 Features 1) Flexible interface usable for multiple standards 2) Low power duty cycle data and clock sub-modes 3) Low analog complexity

27、 4) Low latency data transfer configurable down to 20 ns15) Raw link bandwidth of up to 2.3 Gb/s depending on clocking speed 6) Double data rate (DDR) clocking 7) Rejects 30 dB of interference with the use of differential signaling 8) Low radiated emissions from differential signaling 9) Clocking fr

28、equency (up to 1.1GHz) under the control of FED 10) Supports 0-50 cm line lengths 1Streaming-data latency is affected by the number and word bit length of the streaming words in one RF-BB interface frame. Fewer streaming words and smaller word bit lengths will result in lower latency, but will also

29、lower the bandwidth efficiency of the interface. If bandwidth is abundant, then the latency can be configured to be around 20 ns. JEDEC Standard No. 96A -iv- JEDEC Standard No. 96A Page 1 RADIO FRONT ENDBASEBAND (RF-BB) INTERFACE (From JEDEC Board Ballot JCB-05-105, formulated under the cognizance o

30、f the JC-61 Committee on Wireless Interface Network.) 1 Scope The normative information in this standard is intended to provide a technical design team to construct the interface on a FED and a BED such that they will operate correctly with each other (at the interface level), when designed to this

31、specification. Additional informative information is provided in the appendices to help illustrate the normative material. This document addresses the following interface topics: 1) RF-BB Electrical layer: time and amplitude specifications for lines, drivers, receivers, clocks; 2) RF-BB Link layer:

32、bits, clock-data synchronization, power modes; 3) RF-BB Transport layer: data types, data framing, data bandwidth, connection to core IC; 4) RF-BB Interface Registers. This document defines a high-speed serial link that enables the bi-directional transfer of data and control information between the

33、FED and BED. The document does not mandate the use of specific signaling, standard framing or standard messaging needed to make this an interoperable interface standard for RF devices or BB devices. Figure 1 Interface layer diagram Specific implementations of this interface are beyond the scope of t

34、his standard. JEDEC Standard No. 96A Page 2 2 References 2.1 Informative The following standards contain provisions that, through references in the text, are informative in this standard. At the time of publication, the editions indicated were valid. All standards are subject to revisions. IEEE Std

35、802.11-1999, Wireless Local Area Network (WLAN) Standards, (Reaffirmed 2003) TIA/EIA-644-A, Electrical Characteristics of Low-Voltage Differential Signaling (LVDS) Interface Circuits, February 2001. JESD8-13, Scalable Low-Voltage Signaling for 400 mV (SLVS-400), October 2001. High Speed Serialized A

36、T Attachment rev. 1.0; 29 August 2001 Specification. HyperTransport I/O Link Specification Revision 1.03. 2.2 Normative JEP106M, Standard Manufactures Identification Code, May 2003 3 Terminology For the purpose of this standard, the following terms, definitions, acronyms and abbreviations apply. 3.1

37、 Terms and definitions base-band frequencies: Low frequencies neighboring and including 0 Hz. These frequencies are represented with real In-Phase (I) and Quadrature (Q) parts or together as a complex signal. In this document, the word “base-band” will usually refer to a base-band processor (part of

38、 the BED in this interface). common mode voltage: The average voltage level of the two signals on a differential line. deskew: The act of aligning a clock with incoming data so that the clock edge can be used to latch data in the middle of the data eye. frame: A group of serial bits consisting of a

39、Sync Mark, Header, and one or more of the following fields: 1) streaming data, 2) control data, 3) register data, and 4) parity bit. radio: A device or a group of devices that translates the information bandwidth between base-band and the radio frequency portion of the spectrum. Rx-direction: Direct

40、ion of Receiving from Front End Device to Back End Device. Rx-link: Data link that moves data from Front End Device to Back End Device. TX-direction: Direction of transmitting from the Back End Device to the Front End Device. TX-link: Data link that moves data from Back End Device to Front End Devic

41、e. little endian: The format in which the least significant bit (LSB) of a word is transferred first and the most significant bit is transferred last. JEDEC Standard No. 96A Page 3 3 Terminology (contd) 3.1 Terms and definitions (contd) big endian: The format in which the most significant bit (MSB)

42、of a word is transferred first and the least significant bit is transferred last. TX_IN: Single-ended combination of TX/TXN analog signals received by FED. TX_DATA_VALID (FED): Indication the TX_IN signal contains data for the FED Transport Layer. TX_CLK: Clock signal from FED Link Layer to the FED

43、Transport Layer that has been deskewed for maximum data eye opening on TX_IN. RX_OUT: Single-ended serial data from the FED Transport Layer to the FED Link Layer which is synchronized with CLK_90. RX_DATA_VALID (FED): Indication that the RX_OUT signal contains data for the FED Link layer. CLK_90: 90

44、-degree-offset clock signal provided by the FED Link Layer to the FED Transport layer to synchronize outgoing RX_OUT. LINK_REQUEST: Indication that the Transport layer requires FED Link Layer services. This could also serve as a data clock request. DESKEW_REQUEST: Indication that the Transport layer

45、 needs the Link to deskew incoming data and clocks. One possible reason to send this is because of some CRC error seen in the Transport layer. LINK_STATUS: This signal reports that the Link is ready, or not ready. It is related to DESKEW_STATUS as well. TX_CM_DET: Indication to the FED Link layer fr

46、om the FED Electrical layer that a minimum active common mode voltage has been detected on the TX/TXN lines. RX_EN: Enables the RX/RXN drivers on the FED Electrical Layer to transmit. CLK_0 (FED): FED: Single-ended zero-phase-offset clock from the FED Link layer for the CLK/CLKN driver in the FED El

47、ectrical Layer. CLK_0 (BED): BED: Single-ended clock signal from the BED Electrical Layer to the BED Link Layer corresponding to CLK/CLKN. CLK_EN: Enables the CLK/CLKN drivers on the FED Electrical Layer to transmit. CLK_DET: Indication to the BED Link layer that the BED Electrical Layer has detecte

48、d a minimum active common mode voltage on the CLK/CLKN lines. RX_CM_DET: Indication from the BED Electrical layer to the BED Link Layer that a minimum common mode voltage was detected on the RX/RXN lines. RX_IN: Single-ended analog BED signal corresponding to the received differential RX/RXN signal

49、in the BED Electrical Layer. TX_EN: Enables the TX/TXN drivers in the BED Electrical layer to transmit. TX_OUT: Single-ended data to be driven differentially on TX/TXN. JEDEC Standard No. 96A Page 4 3 Terminology (contd) 3.1 Terms and definitions (contd) TX_DATA_VALID (BED): Indication from the BED Transport Layer that TX_OUT contains valid data for the BED Link Layer. RX_DATA_VALID (BED): Indication that signals from the BED Link layer on RX_IN contains data for the BED Transport Layer. 3.2 Acronyms and abbreviations BED Back-end device. Relative to the RF-BB interface, the BED