KS C IEC 60748-2-2001 Semiconductor devices－integrated circuits－Part 2：Digital integrated circuits《半导体器件 集成电路 第2部分 数字集成电路》.pdf

1、 KSKSKSKS SKSKSKS KSKSKS SKSKS KSKS SKS KS 2001 12 11 http:/www.kats.go.krKS C IEC 60748 2 2： KS C IEC 60748 2： 2001 (2011 ) C IEC 60748 2： 2001 : ( ) ( ) ( ) ( ) : (http:/www.standard.go.kr) ： ： 2001 12 11 ： 2011 12 13 2011-0563 ： ： ( 02-509-7294) (http:/www.kats.go.kr). 10 5 , . C IEC 60748 2： 200

2、1 i . 1 1 1. 1 2. 1 2 1. 1 2. .8 3. 19 4. .31 5. 32 6. .35 7. 35 8. 45 9. (PLD) .46 3 1 1. 46 2. 46 3. ().47 4. ( )48 5. .48 6. MOS .52 7. 53 8. .57 9. ( )57 10. ( )57 11. 57 12. , .57 13. 57 14. 58 1 59 2 A. , / (SRAM, DRAM, ROM) C IEC 60748 2： 2001 ii 1. 60 2. 60 3. ().60 4. ( )60 5. .60 6. MOS 60

3、 7. 60 8. ( ).65 9. ( ).65 10. , .66 11. 66 12. 66 B. ROM 1. 67 2. 67 3. ().67 4. 67 5. 68 6. ( )69 7. .70 8. 70 9. ( ).70 10. ( ).70 11. , .70 12. 70 13. 71 C. (CAM) 1. 72 2. 72 3. 2 A, 3.6. .73 4. 2 A, 7. 7.1 .73 5. 2 A, 7.2, 7.3 .73 6. 2 A, 8.12. .73 3 1. 74 2. 74 3. ().75 C IEC 60748 2： 2001 iii

4、 4. ( )76 5. 76 6. , 78 7. 78 8. 78 4 (PLD) 1. 79 2. 79 3. 79 4. ( )81 5. ( )82 6. 83 7. 84 8. 86 9. , , 86 10. 86 4 1 1. 88 2. 88 3. .88 2 1. H L ( VOH, VOL) 3790 2. H L ( IIH, IIL) 38.91 3. ( IOS) 40.91 4. 41.92 5. () 4893 6. ( VIK) 94.95 7. ( IOZ) 95.96 8. 9697 3 1. 1107 2. 2.108 3. 6, 11.109 4.

5、114 5. 10.131 C IEC 60748 2： 2001 iv 6. 97.133 5 1 1. 135 2. 135 ICS 31.200 KS 2： C IEC 60748 2： 2001(2011 ) Semiconductor devices integrated circuits Part 2： Digital integrated circuits 1997 2 IEC 60748-2(Semiconductor devices Part 2： Digital integrated circuits) . 1 1. . 2. . . , . IEC ISO . IEC 6

6、0747-1： 1983, 1： IEC 60748-1： 1984, 1： IEC 60748-3： 1986, 3： IEC 60748-4： 1987, 4： 2 1. 1.1 . . . . . 1.1.1 , . 1 . , . C IEC 60748 2： 2001 2 2. ( ) . 1.1.2 2 2 1.1.3 (2 ) 2 ( ) “L ” , “L ” . 1.1.4 (2 ) 2 ( ) “H ” , “H ” . 1.1.5 ( ) 1.1.6 3 (sink) , 2 ( ) Z . 1.2 1.2.1 (2 ) ( ) L H 1.2.2 (2 ) ( ) L

7、H , ( ) ( ) (L H ) . 1.2.3 (Function table) . (2 L, H ) . , . . . L/G X . 1.2.4 ( ) (Truth table) . . “ ” “ ” . 1.2.5 (Excitation) ( ) ( ) ( ) . . . 1. . 2. , ( ) . 1.2.6 ( ) (Active level) C IEC 60748 2： 2001 3 1.2.7 ( ) (Active transition) . 1.2.8 ( ) ( ) ( ) ( ) ( ) ( ) ( ) , ( ) . 1.2.9 ( ) ( )

8、( ) ( ) ( ) , ( ) , ( ) . 1.2.10 ( ) ( ) ( ) 1. ( ) , . 2. , ( ) . 1.2.11 () . . , ( ) ( , , ) . 1.2.12 (Preparatory input terminal) ( ) 1.2.13 (Enable input) (active) , 1. “ ” a) . b) “ ” (latch) . 2. “ ” . 1.2.14 (Chip -enable input) (inactive) , 1.2.15 (Chip -select input) , 1.2.16 (Output enable

9、 input) , C IEC 60748 2： 2001 4 , , ( ) . 1.2.17 (Write -enable input) , 1.2.18 (Disable input)； (Inhibit input) , 1. . 2. , . , . 1.2.19 (Level -operated input) ( ) 1.2.20 (Transition -operated input) ( ) 1.2.21 (Set) a) (ISO) . b) (ISO) 0 . “ (reset)” . 1.2.22 (Reset) a) (ISO) . b) (ISO) 0 . “ (se

10、t)” . 1.3 1.3.1 (Digital circuit) 1. “ ” “ ” . 2. ( ) . 1.3.2 2 (Binary circuit) 2 2 . 1.3.3 () Combinational(digital) circuit , 1.3.4 () Sequential(digital) circuit ( , ) . 1.3.5 (Elementary combination circuit) 2 ( ) . H L 1 . 1. ( 1 ) H L 4 . (Boolean) 2 0 1 L H 4 AND, OR, NAND, NOR . C IEC 60748

11、 2： 2001 5 2. (non-elementary combinational circuit) . 1.3.6 (Bistable circuit) ( ) , 1. ( ) , ( ) . 2. ( ) L H . 3. “ ” , . , . “ ” (single excitation bistable circuit) . 1.3.6.1 ( ) Edge -triggered(transition-operated) bistable circuit 1.3.6.2 (Pulse-triggered bistable circuit) , / (negative) . 1.

12、3.6.3 (Data -lock-out bistable circuit) , 1.3.7 (Monostable circuit) ( ) 1. . “ ” ( ) ( ) . 2. / ( ) . 1.3.8 (Expander circuit) 1.3.9 2 (Binary inverter) 2 . L(H) H(L) . 1.3.10 - (Master -slave arrangement) “ ” “ ” . . 1.3.11 (Register) , , . 1.3.12 (Shift register) 1.3.13 (Counter) 1 , 1.3.14 (Digi

13、tal decoder)( ) C IEC 60748 2： 2001 6 ( ) 1.3.15 (Programmable logic device, PLD) 1.3.16 (Programmable logic array, PLA) AND OR 1.3.17 (Programmable gate array, PG/A) 1.4 1.4.1 () (Threshold voltage) (hysteresis) . Vhys VIT+ VIT- Vhys VITP VITN1.4.1.1 () VIT+, VITP 1.4.1 1.4.1.2 () VIT-, VITN 1.4.1

14、1.4.2 (2 ) (Input loading factor) (reference load) , (output loading capability) . 1.4.3 (2 ) (Output loading capability) , . 1.4.4 (Set -up time) 1. . 2. . . 3. , ( ) . 1.4.5 (Hold time) 1. . 2. . . 3. , ( ) . 1.4.6 (Resolution time) C IEC 60748 2： 2001 7 1. . 2. . . 1.4.7 H L (High -level to low-l

15、evel propagation time) L (H ) , , 1. . 2. L H . 1.4.8 H L (High-level to low-level transition time) H (L ) , , 1.4.9 (Enable time) 1.4.10 (Disable time) 1.4.11 (3 ) (Output enable time) 3 ( ) (H, L) , 1.4.12 (3 ) (Output disable time) 3 (H, L) ( ) , 1.4.13 () 1.4.14 (Valid time) 1.4.15 (Output data -valid time) . . 1.4.16 (2 ) () Equivalent input(output) capaci tance