1、ANSI/TIA/EIA-136-131-C-2001 Approved: APRIL 23, 2001 v Fc 53 6 M TIA/EIA STANDARD TDMA Third Generation Wireless - Digital Traffic Channel Layer 3 TIA/EIA- 136- 13 1 -C (Revision of TINEIA-136-13 1-B) APRIL 2001 TELECOMMUNICATIONS INDUSTRY ASSOCIATION The TelecoininLiiiicatioiis Industry Association
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7、tions to applicants desiring to obtain such licenses. Details rnay be obtained from the standards developer. The users attention is called to the possibility that compliance with this document rnay require This Standard does not purport to address all safety problems associated with its use or all a
8、pplicable regulatory requirements. It is the responsibility of the user of this Standard to establish appropriate safety and health practices and to determine the applicability of regulatory limitations before its use. (From Standards Proposal No. 4027- 13 l-C, formulated under the cognizance of the
9、 TIA TR-45.3 Subcommittee on Time Division Digital Technology.) Published by TELECOMMUNICATIONS INDUSTRY ASSOCIATION 2001 Standards and Technology Department 2500 Wilson Boulevard Arlingon, VA 22201 PRICE: Please refer to current Catalog of EIA ELECTRONIC INDUSTRIES ALLIANCE STANDARDS and ENGINEERIN
10、G PUBLICATIONS or call Global Engineering Documents, USA and Canada (1-800-854-7179) International (303-397-7956) All rights reserved Printed in U.S.A. TINEIA-136-131-C Contents 1. Digital Traffic Channel Structure 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 Shortened Burst Definition . 6 Frame Length 6 1
11、.2.1 Standard Offset Reference 8 Gross Rate for the Traffic Channel . 9 1.3.1 n/4 DQPSK . 9 1.3.2 n/4 DQPSK for ACELP (CC2) 9 1.3.3 8-PSK Full-rate 9 1.3.4 8-PSK Half-rate 9 Guard and Power Ramp Up Interval . 9 Synchronization WordTime Slot Identifier . 9 Coded Digital Verification Color Code (CDVCC
12、) 13 Coded Digital Control Channel Locator (CDL) .13 DATA . 14 1.8.1 Channel Encoding . 14 1.8.2 Interleaving. . .15 Pilot Symbols Fields (Pn) 1.5.1 Synchronization WordTime Slot Identifier for 8-PSK Full-Rate Reverse Channel 12 . 16 1.10 Power Ramp (PUMP) .17 1.10.1 .n/4 DQPSK for ACELP (CC2) .17 1
13、.10.2 8-PSK Full-rate and 8-PSK Half Rate 17 1.11 Fast Power Control (F1 and F2) . 17 1.12 Reserved (RSVD) .17 2. Digital Voice and Data Signals - Mobile Station . 19 2.1 2.2 2.3 2.4 2.5 2.6 2.7 Modulation .19 2.1.1 n/4 DQPSK Modulation . 19 2.1.2 8-PSK Modulation . . .22 2.1.3 Modulation Accuracy .
14、 26 Demodulation . 30 2.2.1 n/4 DQPSK Modulation 30 De-Interleaving . 30 Convolutional Decoding Cyclic Redundancy Check (CRC) . 31 Downlink Power Control Requirements . 32 Fast Power Control Requirements. 32 2.7.1 8-PSK Full-rate . . 33 2.7.2 8-PSK Half-rate .34 2.2.2 8-PSK Modulation I TINEIA-136-1
15、31-C 3 . Digital Voice and Data Signals . Base Station . 36 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 Modulation . 36 3.1.1 Channel Sharing 36 3.1.2 n/4 DQPSKModulation 36 3.1.3 8-PSK Modulation . 36 3.1.4 Slot Repetition for n/4 DQPSK and 8-PSK 36 3.1.5 Transmit Diversity for AMR-HR and AMR-FR 37 Demodul
16、ation 3.2.1 n/4 DQPSKModulation Speech Coding 39 De-interleaving . 39 Convolutional Decoding . 40 Speech Decoding 40 Downlink Power Control Requirements . 41 Fast Power Control Requirements 41 Delay Interval Requirements 42 4 . Change History for TIA/EIA-136-131 . 43 II TINEIA-136-131-C Tables Table
17、 1 Sync Word Usage . 11 Table 2 Full-rate Synchronization Sequences 12 Table 3 8-PSK Half Rate Synchronization Sequences . 12 Table 4 8-PSK Symbol Phases . .24 Table 5 Table 6 8-PSK Symbol Mapping in Slot Repetition . .37 38 Modulator to transmit signal path mapping for simple transmit diversity . I
18、 . 111 TINEIA-136-131-C Fig u res Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 TDMA Frame Format . . 1 Full-Rate Time Slot Formats - Mobile Station to Bas
19、e Station . 1 . 2 Half-Rate Time Slot Formats - Mobile Station to Base Station Full-Rate Time Slot Formats - Base Station to Mobile Station . 2 Half-Rate Time Slot Formats - Base Station to Mobile Station . 3 Double-Rate Time Slot Formats-Base Station to Mobile Station . Triple-Rate Time Slot Format
20、s - Mobile Station to Base Station . Triple-Rate Time Slot Formats - Base Station to Mobile Station . Initial Primary and Subsequent Primary Slot Usage . Reverse Time Slot Symbols Standard Offset Reference Phase Constellation . . Differential Encoder . . 20 Transnit Signal Generatio Phase Constellat
21、ion . . Double-Rate Time Slots - Mobile Station to Base Station . . 5 Forward Time Slot Symb . 8 . 8 . 23 . Transnit Signal Generatio Modulator Output to Tran I iv TINEIA-136-131-C Slot 1 8 Slot 2 Slot 3 Slot 4 Slot 5 Slot 6 9 DATA 1. SYNC DATA SACCH CDVCC DATA Digital Traffic Channel Structure G Th
22、is diagram depicts the frame structure: Figure 1 TDMA Frame Format R RSVD SACCH SYNC CDVCC G Note 1: TDMA Frame contains different number of bits depending upon modulation. .n/4 DQPSK = G*(,296 -i- 28) = 1944 bits; 8-PSK hli-rak = 6*(444 -+ 14%) = 2832 bits; 8-PSR laldif-rae = 6*(456 + IPJ) = 2916 b
23、its. R P F P RSVD DATA SYNC SACCH DATA P DATA CDVCC DATA P 112 2 3 Figure 2 Full-Rate Time Slot Formats - Mobile Station to Base Station 6 16 28 122 12 12 122 6 4 12 28 12 DTX Low Truncated Burst n/4 DQPSK Slot Format, (All Numbers indicate bits) 99911 i 96 14svm 12 90 9 90 12 96 9 10 8-PSK Slot For
24、mat (All numbers indicate bits except as noted) 1 TINEIA-136-131-C G 999 i R RSVD FI F2 RSVD SACCH SYNC CDVCC RSVD G RPI FI mz ci 9 93 li 1 12 14sym 12 6 R KSP/D Pi F2 KSP/D SACCH SYNC CDVCG KSP/D SYNC 8-PSK DTX Low Truncated Burst Slot Format (All numbers indicate bits except as noted) SACCH DATA C
25、DVCC DATA RSVD CDL Figure 3 Malf-Rate Time Slot Formats 1 Mobile Station to Base Station SYNC 1 97 10 sym I? 96 9 96 12 96 9 SACCH DATA CDVCC DATA RSVD PUMP 8-$S1; half-rate Slot Forni (Ail inunbers indicate bits except as noted) SYNC DATA CDVCC DATA F RSVD PRAM P Fiaure 4 Full-Rate Time Slot Format
26、s - Base Station to Mobile Station 8 9 10 2 28 142 12 136 1 1 4 .n/4 DQPSK Slot Format for ACELP (CC2) (All numbers indicate bits) TINEIA-136-131-C SYNC 14sym 1 I i 102 9 99 9 99 9 99 9 6 I F F RSVD DATA P1 DATA P2 DATA P3 DATA P4 PUMP 11. P i I 8-PSK Slot Format (All numbers indicate bits except as
27、 noted) P DATA P DATA FI DATA P2 SYNC DATA FI DATA P2 DATA P DAIA P K A 2 A ia A A 3 RB R 3 3R .a, M P 2 Fiqure 5 Half-Rate Time Sbt Formats - Base Station to Mobile Station G 9 102 9 101 i 2 I Ili svm 2 i 2 I is9 is I02 9 6 R DATA SYNC DATA SACCH CDVCC DATA RSVD 3 8-PSK ha1 f-rare Slor tonnat (AU r
28、iurnbsrs indicstc bits sxcept a.: rioted) RSVD DATA SYNC DATA RSVD CDVCC DATA 4 Figure fe Double-Rate Time Slots - Mobile Station to Base Station SYNC 5 SACCH DATA CDVCC DATA RSVD CDL 6 6 16 28 122 12 12 122 Primary Slot Format (All numbers indicate bits) 6 6 16 28 122 12 12 122 Secondary Slot Forma
29、t (All numbers indicate bits) Figure 7 Double-Rate Time Slot Formats-Base Station to Mobile Station 28 12 130 12 130 1 11 8 Primary Slot Format (All numbers indicate bits) 3 TINEIA-136-131-C SYNC 28 12 130 12 130 1 11 RSVD DATA CDVCC DATA RSVD CDL I G 3 R DATA SYNC DATA SACCH CDVCC DATA 4 RSVD 5 RSV
30、D DATA SYNC DATA SACCH CDVCC DATA I RSVD RSVD DATA SYNC DATA RSVD CDVCC DATA Secondary Slot Format (All numbers indicate bits) SYNC Figure 8 Triple-Rate Time Slot Formats - Mobile Station to Base Station SACCH DATA CDVCC DATA RSVD CDL 6 6 16 28 122 12 12 122 Secondary Slot Format Figure 9 Triple-Rat
31、e Time Slot Formats - Base Station to Mobile Station 28 12 130 12 130 1 11 Primary Slot Format (All numbers indicate bits) 28 12 130 12 130 1 11 8 Secondary Slot Format 4 I TINEIA-136-131-C Figure 14% Initial Primary and Subsequent Primary Slot Usage 10 II 12 13 lu1 IP I SI SI SP I SI S TSn TSn+l TS
32、n+2 TSn+3 TSn+4 TSn+5 TSn+6 The Primary slot for multi-rate operation is defined as the first time slot transmitted in a contiguous group of 3 slots The Secondary slot is defined as the one or two slots following the Primary fiist transmitted slot within the same contiguous group of 3 slots. Determi
33、nation of the Primary slot and Secondary slot is given by the Assigned Time Slot information element. For d4 DQPSK the Bit Positions (BP) for DTX Low Truncated Burst Slots are numbered sequentially from 1 to 68. The Bit Positions (BP) of forward and other reverse time slots are numbered sequentially
34、 from 1 to 324. In the forward time slot, the fiist transmitted bit of the SYNC field has BP = 1 and the last transmitted bit of the CDL field has BP = 324. In the reverse time slot, the fiist transmitted bit of the G field has BP = 1. Interpretation of the above fields is as follows: G- R- Pn - F1,
35、 k2 - I:I A, P2 11 FI R, F? R DATA - DnTA n DrITA I SACCH - CDVCC - SYNC - CDL - RSVD - U- IP - SP - S- TSn - PRAMP - Guard Time (see Section 1.4) Ramp Time (see Section 1.4) Pilot Symbols Field n (see Section 1.9) Fast Power Control (See section 1.1 1) Past Xower Cimtroi for half-rate liser A (see
36、secrion I. I 1) Fasr Power Control firr ldf-r I R (see section I. 1 i) User Information or FACCH u, bzL I Inionnalion or PAKH or half-irale user A (see Section i .8) User 1rifomiation or FACCH Slow Associated Control Channel (see TIA/EIA-136-133) Coded Digital Verification Color Code (see Section 1.
37、6 and Synchronization and Training (see Section 1.5) Coded Digital Control Channel Locator (see Section 1.7) Reserved (See section 1.12) Unused Time Slot Initial Primary Slot Subsequent Primary Slot Secondary Slot Time Slot n Power Ramp (see Section 1.10) haif-.rate user E3 (see Secrion i .S TIA/EIA
38、-136-132) 5 TINEIA-136-131-C G1 I 2 3 4 5 6 7 8 9 10 II 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 RSDSDVSDWSDXSDYS G2 30 31 32 33 1 .I Shortened Burst Definition 1.2 The Shortened Burst format is shown in the following figure: The Shortened Burst contains: G1: 3 symbol length guard time.
39、 R: 3 symbol length Ramp time. S: 14 symbol length Sync Word; The mobile station uses its assigned sync word. D: 6 symbol length CDVCC; The mobile station uses its assigned DVCC. G2: 22 Symbol length guard time. Note that the first 3 symbols of G2 consist of RAMP. The fields V,W,X,Y contain bits as
40、follows: v= O000 w= 00000000 x = 000000000000 Y= 0000000000000000 The above format allows determination by the base station of Timing Alignment after detection of any 2 or more sync words of the Shortened Burst. This is because the symbol interval between any two sync words in the above format is un
41、ique to the 2 sync words detected. Determination of the number of symbols between two detected sync words uniquely defines the location of the detected sync words within the received Shortened Burst. Frame Length The mobile station shall derive timing for the transmit symbol and TDMA frame and slot
42、clocks from a common source which shall track the base station symbol rate as perceived at the mobile station receiver. The frequency tracking shall be maintained over all specified operating conditions. The frame length on each digital TDMA RF channel shall be 40 milliseconds. Each frame shall cons
43、ist of six equally sized time slots (1-6), exactly 162 symbols in length. Each full-rate traffic channel shall utilize two equally spaced time slots of the frame (1 two di-bit symbols corresponding to adjacent signal phases differ only in a single bit. Since most probable errors due to noise result
44、in the erroneous selection of an adjacent phase, most di-bit symbol errors contain only a single bit error. Note also, the rotation by .n/4 of the basic QPSK constellation for odd (denoted O) and even (denoted O) symbols. Figure 14 Phase Constellation I The information is differentially encoded; sym
45、bols are transmitted as changes in phase rather than absolute phases. A block diagram of the differential encoder is shown in Figure 15. The binary data stream entering the modulator, bm, is converted by a serial-to- I parallel converter into two separate binary streams (Xk) and (Yk). Starting from
46、bit 1 in time of stream bm, all odd numbered bits form stream xk and all even numbered bits form stream Yk. 19 TINEIA-136-131-C m b O Figure 45 Differential Encoder Differential phase encod i ng Serial -to- parallel Qk converter k Xk 1 O O 1 4 Yk AO -3.n 4 3.n 4 - 1 - 1 O O n - 4 -n - 4 5 6 The digi
47、tal data sequences (Xk) and (Yk) are encoded onto (Ik) and (Qk) according to: Ik = Ik-1 COSA(xk,yk)l - Qk-i SinA(xk,yk)l Qk = Ik-1 SinA(xk,yk)l + Qk-1 COSA(xk,yk)l where Ik-1, Qk-1 are the amplitudes at the previous pulse time. The phase change A is determined according to the following table: The s
48、ignals Ik,Qk at the output of the differential phase encoding block can take one of five values, O, I 1, f - resulting in the constellation shown in Figure 1 il. 1 Jz 20 TINEIA-136-131-C 5 6 I 8 Impulses Ik, Qk are applied to the inputs of the I two three-bit symbols corresponding to adjacent signal phases differ only in a single bit. Since most probable errors due to noise result in the erroneous selection of an adjacent phase, most three-bit symbol errors contain only a single bit error. Also, note that phase transitions between any two symbol phases in Figure 17 are possible. 22
