1、UL COPYRIGHTED MATERIAL NOT AUTHORIZED FOR FURTHER REPRODUCTION ORDISTRIBUTION WITHOUT PERMISSION FROM ULMarch 6, 20081SUBJECT 2569OUTLINE OF INVESTIGATIONFORPART 5: LOW-VOLTAGE SURGE WITHSTAND TELECOMMUNICATIONSLINE FEED RESISTOR (LFR)ISSUE NO. 1MARCH 6, 2008Summary of TopicsThis first issue of the
2、 Outline of Investigation for Low-Voltage SurgeWithstand Telecommunications Line Feed Resistor (LFR), Subject 2569,applies to Line Feed Resistors (LFRs) for up to 600 Vac, 60 A limitedduration current interrupting capability.The UL Foreword is no longer located within the UL Standard. For informatio
3、nconcerning the use and application of the requirements contained in thisStandard, the current version of the UL Foreword is located onULStandardsInfoNet at: http:/ 2008 UNDERWRITERS LABORATORIES INC.UL COPYRIGHTED MATERIAL NOT AUTHORIZED FOR FURTHER REPRODUCTION ORDISTRIBUTION WITHOUT PERMISSION FR
4、OM ULMARCH 6, 2008SUBJECT 25692No Text on This PageUL COPYRIGHTED MATERIAL NOT AUTHORIZED FOR FURTHER REPRODUCTION ORDISTRIBUTION WITHOUT PERMISSION FROM ULCONTENTS1.0 General 41.1 Scope .43.0 Service Environment Conditions .47.3 Evaluation exception .10MARCH 6, 2008 SUBJECT 2569 3UL COPYRIGHTED MAT
5、ERIAL NOT AUTHORIZED FOR FURTHER REPRODUCTION ORDISTRIBUTION WITHOUT PERMISSION FROM UL1.0 GeneralNote: This Part is intended to be read together with Low-Voltage Surge Withstand TelecommunicationsOvercurrent Protector Components Part 1: General Requirements, hereafter referred to as Part 1. Thenumb
6、ering of the Clauses in this Part corresponds to like numbered Clauses in Part 1. The requirementsof Part 1 apply unless modified by this Part.1.1 ScopeThis Part applies to Line Feed Resistors (LFRs) for up to 600 Vac, 60 A limited duration currentinterrupting capability.3.0 Service Environment Cond
7、itions3.1 Equipment in controlled areas must be capable of meeting manufacturers requirements for ambienttemperature range of +5C to +40C. LFRs used in this equipment shall continue to meet therequirements of this standard for temperatures between +5C and +70C. For environments outside the+5C to +40
8、C range, the manufacturer shall be contacted to obtain temperature derating factors.3.2 Equipment in uncontrolled areas must be capable of meeting manufacturers requirements for anambient temperature range of -40C to +70C. (Includes effects of solar loading) Protectors used in thisequipment shall co
9、ntinue to meet the requirements of this standard for temperatures between -40C and+85C. For environments outside the +5C to +40C range, the manufacturer shall be contacted to obtaintemperature derating factors.3.3 The LFR derating factor depends on several things. When the current interruption is ca
10、used bysubstrate fracture due to high temperature, there will be relatively small derating with increased ambienttemperature. When the current interruption or reduction is caused by supplementary series elements,such as a solder link or a PTC thermistor, the rated current will decrease with increasi
11、ng ambienttemperature at about 0.5 percent/C. Many LFRs are manufactured as dual elements. In themedium-term, the operating current is independent if one or two elements are powered. For a few cyclesand in the long-term the operating current is more dependent on the number of powered elements, seeFi
12、gure 5.1.This is generated text for figtxt.MARCH 6, 2008SUBJECT 25694UL COPYRIGHTED MATERIAL NOT AUTHORIZED FOR FURTHER REPRODUCTION ORDISTRIBUTION WITHOUT PERMISSION FROM UL7.1.3 Physical test arrangement of the DUTThe high power loss and temperature rise of an LFR mandates that the LFR shall be mo
13、unted and testedin an environment similar to the end application to obtain meaningful measurements. LFRs operate at hightemperatures and the cheesecloth temperature indicator must not contact the LFR otherwise a falseindication will be given.EIA/JESD51, Methodology for the Thermal Measurement of Com
14、ponent Packages and appropriate partsin the JEDEC EIA/JESD51 series provides a standardized method of mounting surface mount andthrough-hole components on defined area and material PCBs in a test enclosure. Typically, the physicalarrangement of a thick-film ceramic substrate LFR is a SIP (Single-In-
15、Line) format or multiple SIPs in acarrier frame.JESD51 test enclosureThe test enclosure shall be as defined in JESD51-2, which outlines the environmental conditionsnecessary to ensure accuracy and repeatability component performance in natural convection. Theenclosure shall be a box with an inside d
16、imension of 1 ft3(0.0283 m3), see Figures 5.2. All seams shouldbe thoroughly sealed to ensure no airflow through the enclosure. The construction materials shall be lowconductance, such as cardboard, polycarbonate, polypropylene, wood, and plywood and of 1/8 inch(3.175 mm) minimum wall thickness.This
17、 is generated text for figtxt.NOTE: The operating current curve, above, is an example only.Figure 5.1 LFR operation: Ceramic Only (co), Fused Ceramic (f), Single (s) and Dual (d) elementpoweringMARCH 6, 2008 SUBJECT 2569 5UL COPYRIGHTED MATERIAL NOT AUTHORIZED FOR FURTHER REPRODUCTION ORDISTRIBUTION
18、 WITHOUT PERMISSION FROM ULJESD51 test fixtureTwo fixtures are required, one for vertical PCB mounting (see Figure 5.2) and the other for horizontal PCBmounting (see Figure 5.3).The test fixture shall be as defined in JESD51-2, but increased in height by 1.5 in to accommodate verticalPCB mounting. T
19、he fixture gives support and location to the PCB and thermocouple ensuring that thecomponent is positioned in the geometric centre of the enclosure. The material used for the fixture shallbe of 0.5 in insulating material and have a low thermal conductance.This is generated text for figtxt.Figure 5-2
20、 Enclosure Cube with vertical PCB fixtureMARCH 6, 2008SUBJECT 25696UL COPYRIGHTED MATERIAL NOT AUTHORIZED FOR FURTHER REPRODUCTION ORDISTRIBUTION WITHOUT PERMISSION FROM ULFigure 5.3 Fixture with horizontal PCBMARCH 6, 2008 SUBJECT 2569 7UL COPYRIGHTED MATERIAL NOT AUTHORIZED FOR FURTHER REPRODUCTIO
21、N ORDISTRIBUTION WITHOUT PERMISSION FROM ULJESD51 PCBThe FR4 material PCB size shall be 101.5 mm x 114.5 mm 0.25 mm as defined in JESD51-10. A typicaledge connector is depicted in Figure 5-4. The edge connector can be pin-out and pitch modified forspecific needs. Multiple rows of vias along the edge
22、 connector are allowed. The board finish thicknessshall be 1.60 mm 0.16 mm. Copper traces shall be 70 m 14 m thick with a finished trace width of 2.0mm 0.2 mm. This combination of copper track thickness and width gives an ampacity equivalent to 26AWG. Lands and plated through-hole vias for package o
23、r clip mounting shall comply with the relevantANSI/IPC-2221A, ANSI/IPC-2222: and IPC-SM-782A design standards.This is generated text for figtxt.Flared tracesThe total trace width connecting to one package terminal shall be 2.0 mm 0.2 mm. Traces should be laidout such that the test device will be cen
24、tered relative to a 101.5 mm x 101.5 mm section towards the topof the board (away from the edge connector). The traces connecting to the package must extend at least25 mm out from the edge of the device body. Trace lengths longer than this are allowed. Traces must berouted in a radial fashion (flare
25、d) to meet the edges of a rectangle such that the terminal via locations areequally spaced over 90% of the perimeter of the sides of this rectangle. Traces must be flared out to the25 mm perimeter adjacent to the side of the package on which they originate.A single PCB design can be used for a famil
26、y of packages with the same pin pitch as long as the tracesare fanned out to meet the requirements for the largest body size. Multiple components can be mountedon a single board up to the number permitted by the layout guidelines (see Figure 5.5). For packages witha single row of leads, the odd numb
27、ered pins should be fanned out to one side of the pattern and the evennumbered pins should fan out to the opposing side.Figure 5.4 Example of PCB outer dimensions and edge connector design.MARCH 6, 2008SUBJECT 25698UL COPYRIGHTED MATERIAL NOT AUTHORIZED FOR FURTHER REPRODUCTION ORDISTRIBUTION WITHOU
28、T PERMISSION FROM ULThe plated through-hole vias at the border of the trace fan-out area and beyond shall have a solder landof no less than 1.25 mm diameter with a drill hole of no less than 0.85 mm diameter.This is generated text for figtxt.Hard wiringLink wires, used to connect the fan-out trace t
29、o the edge connector shall be made with 22 AWG copperwires.Cheesecloth hazard indicator applicationTwo single plies of cheesecloth shall be wrapped tightly around the PCB spaced off of the top and bottomsurfaces by the following distances: PCB component side: Whichever is the greater height of 12.5
30、mm above the surface or 6.25mm above the top of the component PCB non-component side: 6.25 mm above the surfaceA suitable framework may be used to support the cheesecloth at the perimeter of the PCB. This treats thePCB as a circuit pack tested as a stand-alone assembly or subassembly, the cheeseclot
31、h encloses thevolume normally allocated to the circuit pack under test.IPC component grid courtyardFigure 5.5 Through-hole SIP LFR tracking and land example on JESD51 PCBMARCH 6, 2008 SUBJECT 2569 9UL COPYRIGHTED MATERIAL NOT AUTHORIZED FOR FURTHER REPRODUCTION ORDISTRIBUTION WITHOUT PERMISSION FROM
32、 ULA PCB land is a portion of a conductive pattern usually, but not exclusively, used for the connection, orattachment, or both of components. A land pattern is a combination of lands intended for the mounting,interconnection and testing of a particular component. Component grid courtyards are inten
33、ded toencompass the land pattern, the component body (centred on the land pattern) and provide adequateclearance for conductive parts, e.g. component terminals. When placing parts on a printed board, thehighest density is when one courtyard touches another. Courtyards use a grid of 0,05 mm and areex
34、pressed as a rectangular area of grid elements. For example a 4x6 courtyard is equal to an area of 2,00mm by 3,00 mm.7.2.3.4 Test circuit configurations for LFRAs LFRs often have multiple fusing resistors for multiple conductor protection, testing must then be doneon an LFR with a single resistor po
35、wered and repeated on another LFR with all the resistors powered.For longitudinal testing both elements shall be simultaneously tested. Transverse testing shall connect theterminals of the untested element to the test generator return. Figure 5.6 illustrates some testconfiguration examples.Impulse t
36、esting shall monitor the LFR for the occurrence of flashover, which could result in hazardouscurrents. Appropriate safeguards must be used in testing. Hazards can result from componentfragmentation and high operating temperatures.This is generated text for figtxt.7.3 Evaluation exceptionEvaluation criterion 7.1.6.4 does not apply the tests that cause LFR operation by substrate fracture.Figure 5.6 Current limiter test circuit configurationsMARCH 6, 2008SUBJECT 256910
