1、,2,CAD Tools for Variation Tolerance,David Blaauw and Kaviraj ChopraUniversity of Michigan,-3-,Variability Tolerant CAD Re-Tooling,Goal: Make designs tolerant to process variation,Variation tolerant CAD Tools,-4-,Research in SSTA,SSTA paper count in DAC,Major focus on addition and max function in ar
2、rival time propagation,MAX,-5-,Current Functionality of STA,STA development since 1982 PERT analysis Slope / Delay Modeling False Path Analysis Transparent Latches Clocking Signal Pruning Interconnect Modeling Multiple Input Switching,-6-,Challenges for SSTA,Modeling data for SSTA Which process para
3、meters are most critical to model ? Leff, Vth, Tox, doping, ILD thickness, metal thickness, metal width.,Tracking process as it matures,Obtaining inter-die Variation, Intra-die Variation and spatial information from raw data.,Representing variation in the cell library,-7-,Introduction Statistical Pe
4、rformance Analysis Tools,Credibility ? Discrepancies?,Deterministic,Statistical,Timing Toolbox,Initial Adoption?,-8-,Conventional Deterministic Timing Optimization,Path Delay Distribution,Tmax99 tmax,-9-,Impact of recovering power through sizing, restructuring,Low Power Optimization Uncertainty,Tmax
5、,P,delay,Pre Optimization,Tmax99,-10-,Low Power Optimization Uncertainty,For a single transistor: 10% in Ld 300% in leakage For a full chip: 20X variation in total leakage,10% Ld,100% Isub,Borkar 02,-11-,Optimization objective,Joint power delay probability distribution Maintains correlations between
6、 power and delay Allows computation of yield,-12-,Conclusion,Significant research still needed for complete SSTA solutionKey challenge in obtaining data for SSTA Annotating library information Track process Find most likely adoption point for statistical solutions Opportunity in statistical optimization for yield enhancement Must model both leakage and delay,
