1、BSI Standards Publication Device embedded substrate Guidelines Data format PD IEC/PAS 62878-2-5:2015National foreword This Published Document is the UK implementation of IEC/PAS 62878-2- 5:2015. The UK participation in its preparation was entrusted to Technical Committee EPL/501, Electronic Assembly
2、 Technology. A list of organizations represented on this committee can be obtained on request to its secretary. This publication does not purport to include all the necessary provisions of a contract. Users are responsible for its correct application. The British Standards Institution 2015. Publishe
3、d by BSI Standards Limited 2015 ISBN 978 0 580 90139 3 ICS 31.180; 31.190 Compliance with a British Standard cannot confer immunity from legal obligations. This Published Document was published under the authority of the Standards Policy and Strategy Committee on 31 August 2015. Amendments/corrigend
4、a issued since publication Date Text affected PUBLISHED DOCUMENT PD IEC/PAS 62878-2-5:2015 IEC PAS 62878-2-5 Edition 1.0 2015-08 PUBLICLY AVAILABLE SPECIFICATION PRE-STANDARD Device embedded substrate Guidelines Data format INTERNATIONAL ELECTROTECHNICAL COMMISSION ICS 31.180; 31.190 ISBN 978-2-8322
5、-2808-1 Registered trademark of the International Electrotechnical Commission Warning! Make sure that you obtained this publication from an authorized distributor. colour inside PD IEC/PAS 62878-2-5:2015 2 IEC PAS 62878-2-5:2015 IEC 2015 CONTENTS FOREWORD . 4 1 Scope 6 1.1 Purpose 7 1.2 Applicable r
6、ange . 7 1.2.1 Product 7 1.2.2 Process . 8 1.3 Features . 9 1.3.1 Maintenance of the device embedded substrate structure 9 1.3.2 Maintenance of SiP interposer structure 10 1.3.3 Maintenance of design data with a virtual layer of terminal positions of embedded device(s) 10 1.3.4 Maintenance of termin
7、al structure and embedded device structure including SiP . 11 1.3.5 Seamless ownership of design data . 11 2 File description 12 2.1 File description summary 12 2.1.1 Types of data and their structure . 12 2.1.2 File structure . 14 2.2 3D expression . 15 2.2.1 Coordinates . 15 2.2.2 Position descrip
8、tion . 16 2.2.3 Relation between coordinate origin and board position 16 2.3 Layer concept . 17 2.4 Substrate data 17 2.4.1 Layer map information . 18 2.4.2 Device arrangement information 19 2.4.3 Basic figures 21 2.4.4 Net information 28 2.4.5 Artwork information 29 2.4.6 Package information 29 2.4
9、.7 External port information 29 2.4.8 Internal port information . 29 2.4.9 User expansion information . 29 2.5 Defined data . 29 2.5.1 Layer definition 30 2.5.2 Land definition . 30 2.5.3 Via definition . 31 2.5.4 Device definition 32 2.5.5 User expansion definition 33 3 Terminology. 34 4 Commentary
10、 Additional information 36 Figure 1.1 Flow chart of design of device embedded substrate 7 Figure 1.2 General concept of product . 8 Figure 1.3 Example of a structure of a device embedded substrate 10 Figure 1.4 Examples of a structure of a SiP interposer . 10 PD IEC/PAS 62878-2-5:2015IEC PAS 62878-2
11、-5:2015 IEC 2015 3 Figure 1.5 Example of a laying terminal position of an embedded device in a virtual layer 11 Figure 1.6 Example of showing structures of device embedding and terminals . 11 Figure 1.7 Example of showing structures of SiP and of a device embedding substrate 12 Figure 2.1 Data struc
12、ture . 14 Figure 2.2 One file structure (recommended) . 15 Figure 2.3 Two-File structure . 15 Figure 2.4 Definition of coordinates 16 Figure 2.5 Position definition 16 Figure 2.6 Relation between coordinates and board position 17 Figure 2.7 Layer concept . 17 Figure 2.8 Construction of mounting laye
13、rs 18 Figure 2.9 Construction in the case of omission of mounting layers 19 Figure 2.10 Layer definition in pad connection . 20 Figure 2.11 Layer definition in via connection 20 Figure 2.12 XYZ axes rotation direction . 21 Figure 2.13 Point . 22 Figure 2.14 Area shapes 23 Figure 2.15 Area shapes 23
14、Figure 2.16 Letter data. 24 Figure 2.17 Text shape 24 Figure 2.18 Bonding wire information . 25 Figure 2.19 Wire bonding shape 25 Figure 2.20 Rectangular prismoid 26 Figure 2.21 Examples of via specification 27 Figure 2.22 Device definition 27 Figure 2.23 Example of group such as dimension lines 28
15、Figure 2.24 Data structure of net information . 28 Figure 2.25 Relation of layer definition data . 30 Figure 2.26 Land definitions . 31 Figure 2.27 Relation between hole information and land information 32 Figure 2.28 Definitions of SiP, module and MEMS . 33 Figure 2.29 Definitions of package and mo
16、ld components 33 Table 1.1 Information required in production 9 Table 2.1 List of data . 13 PD IEC/PAS 62878-2-5:2015 4 IEC PAS 62878-2-5:2015 IEC 2015 INTERNATIONAL ELECTROTECHNICAL COMMISSION _ DEVICE EMBEDDED SUBSTRATE GUIDELINES DATA FORMAT FOREWORD 1) The International Electrotechnical Commissi
17、on (IEC) is a worldwide organization for standardization comprising all national electrotechnical committees (IEC National Committees). The object of IEC is to promote international co-operation on all questions concerning standardization in the electrical and electronic fields. To this end and in a
18、ddition to other activities, IEC publishes International Standards, Technical Specifications, Technical Reports, Publicly Available Specifications (PAS) and Guides (hereafter referred to as “IEC Publication(s)”). Their preparation is entrusted to technical committees; any IEC National Committee inte
19、rested in the subject dealt with may participate in this preparatory work. International, governmental and non-governmental organizations liaising with the IEC also participate in this preparation. IEC collaborates closely with the International Organization for Standardization (ISO) in accordance w
20、ith conditions determined by agreement between the two organizations. 2) The formal decisions or agreements of IEC on technical matters express, as nearly as possible, an international consensus of opinion on the relevant subjects since each technical committee has representation from all interested
21、 IEC National Committees. 3) IEC Publications have the form of recommendations for international use and are accepted by IEC National Committees in that sense. While all reasonable efforts are made to ensure that the technical content of IEC Publications is accurate, IEC cannot be held responsible f
22、or the way in which they are used or for any misinterpretation by any end user. 4) In order to promote international uniformity, IEC National Committees undertake to apply IEC Publications transparently to the maximum extent possible in their national and regional publications. Any divergence betwee
23、n any IEC Publication and the corresponding national or regional publication shall be clearly indicated in the latter. 5) IEC itself does not provide any attestation of conformity. Independent certification bodies provide conformity assessment services and, in some areas, access to IEC marks of conf
24、ormity. IEC is not responsible for any services carried out by independent certification bodies. 6) All users should ensure that they have the latest edition of this publication. 7) No liability shall attach to IEC or its directors, employees, servants or agents including individual experts and memb
25、ers of its technical committees and IEC National Committees for any personal injury, property damage or other damage of any nature whatsoever, whether direct or indirect, or for costs (including legal fees) and expenses arising out of the publication, use of, or reliance upon, this IEC Publication o
26、r any other IEC Publications. 8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is indispensable for the correct application of this publication. 9) Attention is drawn to the possibility that some of the elements of this IEC Publication m
27、ay be the subject of patent rights. IEC shall not be held responsible for identifying any or all such patent rights. A PAS is a technical specification not fulfilling the requirements for a standard, but made available to the public. IEC PAS 62878-2-5 was submitted by the JPCA (Japan Electronics Pac
28、kaging and Circuits Association) and has been processed by IEC technical committee 91: Electronics assembly technology. It is based on JPCA-EB02 (2011). It is published as a double-logo IEC / JPCA PAS. The text of this PAS is based on the following document: This PAS was approved for publication by
29、the P-members of the committee concerned as indicated in the following document Draft PAS Report on voting 91/1257/PAS 91/1264/RVD Following publication of this PAS, which is a pre-standard publication, the technical committee or subcommittee concerned may transform it into an International Standard
30、. PD IEC/PAS 62878-2-5:2015IEC PAS 62878-2-5:2015 IEC 2015 5 This PAS shall remain valid for an initial maximum period of 3 years starting from the publication date. The validity may be extended for a single period up to a maximum of 3 years, at the end of which it shall be published as another type
31、 of normative document, or shall be withdrawn. IMPORTANT The colour inside logo on the cover page of this publication indicates that it contains colours which are considered to be useful for the correct understanding of its contents. Users should therefore print this document using a colour printer.
32、 PD IEC/PAS 62878-2-5:2015 6 IEC PAS 62878-2-5:2015 IEC 2015 DEVICE EMBEDDED SUBSTRATE GUIDELINES DATA FORMAT 1 Scope This part of IEC 62878 defines the data format for active and passive devices embedded inside an organic board whose electrical connections are made by means of a via, electroplating
33、, conductive paste or printing of conductive material. The basic structures, the terminology, reliability tests and a design guide are described in the “Standard of device embedded substrate“, JPCA EB01, fourth edition. A device embedded substrate contains device(s) in the board and is connected in
34、a 3D way. Conventional 2D design technology using GERBER format cannot describe all the connection information in a device embedded substrate. We have several proposals to express 3D data formats but they cannot describe the structures given in EB01. The JPCA Committee for standardization of device
35、embedded substrates has studied various formats and developed a format, FUJIKO V-1.0, which can express substrate design data in CAM data used in actual production. This Publicly Available Specification (PAS) described the FUJIKO data format. Figure 1.1 shows the design flow of a device embedded sub
36、strate. The design data can be directly sent to a board manufacturing system using the FUJIKO format, or can be converted to CAM data and then be used in production. The data contain 3D information of coordinates and shapes of devices used. It is possible to check the status of device embedding in a
37、 board, and also make it a common knowledge in production know-how of a production line. This PAS describes the expression of 3D data information, the concept of layers, the structure of board data, and definitions of information repeatedly used in design. PD IEC/PAS 62878-2-5:2015IEC PAS 62878-2-5:
38、2015 IEC 2015 7 Others Embedded board Machine CAD Design document Library Library Equipment Data Equipment Data Equipment Data DXF GERBER Fabrication process CAM Circuit CAD FUJIKO CAM Board CAD FUJIKO Others Embedded board Embedded board Machine CAD Design document Design document Library Library L
39、ibrary Library Equipment Data Equipment Data Equipment Data DXF GERBER Fabrication process Fabrication process CAM Circuit CAD FUJIKO CAM Board CAD FUJIKOFigure 1.1 Flow chart of design of device embedded substrate 1.1 Purpose This file format describes the detailed 3D information of the following e
40、lectronic circuit boards including device embedded substrate and SiP (system in package), and makes it possible to use necessary information from the stage of design to fabrication of products. 1.2 Applicable range 1.2.1 Product It is possible to maintain the following design information of device e
41、mbedded substrate as shown in Figure 1.2. 1) Information of inside device embedded substrate and surface mounting. 2) Assembly information of SiP (System in Package). PD IEC/PAS 62878-2-5:2015 8 IEC PAS 62878-2-5:2015 IEC 2015 A B C D D G E F F C G A B C D D G E F F C GA Embedded active device E Inn
42、er pattern B Surface mounted active device F Surface pattern C Surface mounted passive device G Solder resist D Layer connecting via A C E F B D E F A C E F B D E FA CSP D Wire bonding B Bare die semiconductor device E Interposer C Solder ball F Solder ball Figure 1.2 General concept of product 1.2.
43、2 Process The format describes maintained and available information of each stage in production as described in Figure 1.1 1) Design 2) Simulation 3) Substrate fabrication 4) Device embedding 5) Test. PD IEC/PAS 62878-2-5:2015IEC PAS 62878-2-5:2015 IEC 2015 9 Table 1.1 Information required in produc
44、tion Process Holding data of Data available for Design Circuit Components Shape of the board Board structure Design/Production rule (for check) Limited condition Net list Simulation Circuit Characteristics of components Board properties (materials) Board structure Art work Electrical properties Ther
45、mal properties Mechanical properties Electronic properties Additional information in production Substrate fabrication Art work Drilling Symbol marks Panel format Equipment Additional information in production Device embedding Component shape Embedding position Interconnection terminals Symbol marks
46、Equipment Relative positions of component Component list Test Art work Component shape Component position Terminal information Marks Electrical test equipment Video image inspection 1.3 Features Data format has the following characteristics: 1) can contain the structure of the device embedding subst
47、rate specified inEB01; 2) can contain information of SiP in general (chip stack, PoP TSV, wire bonding, flip-chip, interposer, etc.); 3) design data of terminal positions of embedding device in a virtual layer specified in EB01; 4) information of internal structure of devices such as SiP which canno
48、t be described as a structure of a device embedded substrate and of a terminal structure as 3D design data; 5) seamless keeping of design data of devices having different level such as SiP and of embedding substrate. 1.3.1 Maintenance of the device embedded substrate structure It is possible to keep
49、 and illustrate the 3D structure of device embedded substrate as shown in Figure 1.3. It is also possible to check its 3D structure. PD IEC/PAS 62878-2-5:2015 10 IEC PAS 62878-2-5:2015 IEC 2015 A Embedded active device D Pad connection B Embedded passive device E Space without board material C Via connection Figure 1.3 Example of a structure of a device embedded substrate 1.3.2 Maintenance of SiP interposer struc
