1、 IEEE Standard for a Mixed-Signal Test Bus Sponsored by the Test Technology Standards Committee IEEE 3 Park Avenue New York, NY 10016-5997 USA 18 March 2011 IEEE Computer Society IEEE Std 1149.4-2010 (Revision of IEEE Std 1149.4-1999)IEEE Std 1149.4TM-2010 (Revision of IEEE Std 1149.4-1999) IEEE Sta
2、ndard for a Mixed-Signal Test Bus Sponsor Test Technology Standards Committee of the IEEE Computer Society Approved 9 December 2010 IEEE-SA Standards Board Approved 17 June 2011 American National Standards Institute Abstract: The testability structure for digital circuits described in IEEE Std 1149.
3、1-2001 has been extended to provide similar facilities for mixed-signal circuits. The architecture is described, together with the means of control of and access to, both analog and digital test data. Sample implementation and application details (which are not part of the standard) are included for
4、 illustration. Also, extensions to the standard BSDL are defined that allow description of key component-specific aspects of such testability features. Keywords: analog test, board testing, boundary scan, BSDL, design for testability, IEEE 1149.4, in-circuit test, mixed-signal test The Institute of
5、Electrical and Electronics Engineers, Inc. 3 Park Avenue, New York, NY 10016-5997, USA Copyright 2011 by the Institute of Electrical and Electronics Engineers, Inc. All rights reserved. Published 18 March 2011. Printed in the United States of America. IEEE is a registered trademark in the U.S. Paten
6、t +1 978 750 8400. Permission to photocopy portions of any individual standard for educational classroom use can also be obtained through the Copyright Clearance Center. iv Copyright 2011 IEEE. All rights reserved. Introduction This introduction is not part of IEEE Std 1149.4-2010, IEEE Standard for
7、 a Mixed-Signal Test Bus. The development of this standard began with a preliminary meeting in the summer of 1991 when the need was recognized for a standardized structure to be incorporated into mixed-signal circuits to combat the testability problems posed by such circuits. This meeting adopted th
8、e following mission: To define, document, and promote the use of a standard mixed-signal test bus that can be used at the device and assembly levels to improve the controllability and observability of mixed-signal designs and to support mixed-signal built-in test structures in order to reduce both t
9、est development time and testing costs and to improve test quality. Notice to users Laws and regulations Users of these documents should consult all applicable laws and regulations. Compliance with the provisions of this standard does not imply compliance to any applicable regulatory requirements. I
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15、EE Standards Association or the IEEE standards development process, visit the IEEE-SA web site at http:/standards.ieee.org. v Copyright 2011 IEEE. All rights reserved. Errata Errata, if any, for this and all other standards can be accessed at the following URL: http:/standards.ieee.org/reading/ieee/
16、updates/errata/index.html. Users are encouraged to check this URL for errata periodically. Interpretations Current interpretations can be accessed at the following URL: http:/standards.ieee.org/reading/ieee/interp/ index.html. Patents Attention is called to the possibility that implementation of thi
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19、f this standard are expressly advised that determination of the validity of any patent rights, and the risk of infringement of such rights, is entirely their own responsibility. Further information may be obtained from the IEEE Standards Association. vi Copyright 2011 IEEE. All rights reserved. Part
20、icipants At the time this standard was submitted to the IEEE-SA Standards Board for approval, the Mixed-Signal Test Bus Working Group had the following membership: Bambang Suparjo, Chair Heiko Ehrenberg, Vice Chair Adam Cron Marc Hunter Adam W. Ley Keith Lofstrom Kenneth P. Parker Zafar Quadri Steph
21、en SunterThe following members of the individual balloting committee voted on this standard. Balloters may have voted for approval, disapproval, or abstention. Keith Chow C. Clark Adam Cron Thomas Dineen Heiko Ehrenberg Randall Groves John Harauz Werner Hoelzl Philippe LeBourg Adam Ley Greg Luri Jef
22、frey Moore Kenneth Parker Ulrich Pohl Mike Ricchetti Gordon Robinson Robert Robinson Bartien Sayogo Gil Shultz Michael Stora Walter Struppler Stephen Sunter Bambang Suparjo David Thompson Oren Yuen When the IEEE-SA Standards Board approved this standard on 9 December 2010, it had the following membe
23、rship: Robert M. Grow, Chair Richard H. Hulett, Vice Chair Steve M. Mills, Past Chair Judith Gorman, Secretary Karen Bartleson Victor Berman Ted Burse Clint Chaplin Andy Drozd Alexander Gelman Jim Hughes Young Kyun Kim Joseph L. Koepfinger* John Kulick David J. Law Hung Ling Oleg Logvinov Ted Olsen
24、Ronald C. Petersen Thomas Prevost Jon Walter Rosdahl Sam Sciacca Mike Seavey Curtis Siller Don Wright *Member Emeritus Also included are the following nonvoting IEEE-SA Standards Board liaisons: Satish Aggarwal, NRC Representative Richard DeBlasio, DOE Representative Michael Janezic, NIST Representa
25、tive Julie Alessi IEEE Standards Program Manager, Document Development Michael Kipness IEEE Standards Program Manager, Technical Program Development vii Copyright 2011 IEEE. All rights reserved. Contents 1. Overview 1 1.1 Organization of the standard 1 1.2 Context 2 1.3 Scope . 3 1.4 Background read
26、ing. 6 2. Normative references 6 3. Definitions, acronyms, abbreviations, and voltage symbols. 6 3.1 Definitions . 6 3.2 Acronyms and abbreviations . 10 3.3 Voltage source symbols. 11 4. Testability architecture . 11 4.1 Overview . 11 4.2 TAP controller . 13 4.3 ATAP. 14 4.4 Register architecture 15
27、 5. Instructions . 16 5.1 General 16 5.2 Response of test logic to instructions 17 5.3 Mandatory instructions 17 5.4 Optional instructions 20 6. The TBIC 25 6.1 General 25 6.2 Test bus and TBIC structure 26 6.3 Control of the TBIC. 30 6.4 Differential I/O 33 6.5 Partitioned internal test bus structu
28、re. 34 7. The boundary-scan structure 38 7.1 Structure 38 7.2 DBMs 39 7.3 ABMs 41 7.4 Differential ABMs. 51 8. Measurement methodology 57 8.1 Interconnect testing 57 8.2 Extended interconnect testing 60 8.3 Network measurements . 64 9. Analog parametric limits 65 9.1 General 65 9.2 Switch limitation
29、s 65 9.3 Electrostatic protection 66 9.4 Performance specifications 67 9.5 Measuring performance. 69 9.6 Calibration and errors 76 viii Copyright 2011 IEEE. All rights reserved. 10. Conformance and documentation requirements . 78 10.1 Conformance . 78 10.2 General documentation 79 10.3 Documentation
30、 of residual elements 82 10.4 BSDL Documentation . 84 Annex A (informative) Bibliography . 106 1 Copyright 2011 IEEE. All rights reserved. IEEE Standard for a Mixed-Signal Test Bus IMPORTANT NOTICE: This standard is not intended to ensure safety, security, health, or environmental protection. Implem
31、enters of the standard are responsible for determining appropriate safety, security, environmental, and health practices or regulatory requirements. This IEEE document is made available for use subject to important notices and legal disclaimers. These notices and disclaimers appear in all publicatio
32、ns containing this document and may be found under the heading “Important Notice” or “Important Notices and Disclaimers Concerning IEEE Documents.” They can also be obtained on request from IEEE or viewed at http:/standards.ieee.org/IPR/disclaimers.html. 1. Overview 1.1 Organization of the standard
33、This standard is divided into ten clauses. Clause 1 describes the scope and objectives of the standard and explains how the material of the standard is organized. Clause 2 lists references to related standards necessary for the understanding of this standard, while Clause 3 defines terms and acronym
34、s. Clause 4 through Clause 8 contain specifications for the particular features of this standard and contain descriptive material that illustrates the need for the specified features or their application. This descriptive material is intended to place the details of various parts of the design in pe
35、rspective and to provide examples of implementation and use. Clause 9 addresses some of the practical issues that will arise in the implementation of the standard. In particular, it defines the performance required from a compliant part and describes how the performance limits can be measured. Claus
36、e 10 summarizes the conditions under which any particular component can claim conformance to the standard and defines the documentation that shall be provided by the manufacturer to allow test equipment to make use of the test features. This clause also defines extensions to BSDL for describing conc
37、epts and structures introduced by this standard. IEEE Std 1149.4-2010 IEEE Standard for a Mixed-Signal Test Bus 2 Copyright 2011 IEEE. All rights reserved. 1.2 Context Figure 1 illustrates the context within which this standard is intended to operate. It shows an electrical circuit constructed as a
38、printed circuit assembly (PCA) consisting of a substrate carrying a pattern of conductors (the interconnect) on which separately manufactured components are mounted so that the component pins make electrical contact with the interconnect. In normal functional operation, the PCA connects to other par
39、ts of the system by way of a set of contacts, such as the edge-connector shown in Figure 1. Figure 1 Mixed-signal printed circuit assembly In Figure 1, the component that is the subject of this standard is shown shaded. In a typical mixed-signal analog and digital PCA, the pins of the component may
40、be connected to: Other mixed-signal components (labeled M), which may or may not conform to this standard; Digital components (labeled D), which may or may not conform to IEEE Std 1149.1TM-2001;1 Analog components (labeled A), which could be anything from a single transistor to an operational amplif
41、ier or an analog signal processing circuit, but which would be unlikely to contain any associated testability features; or Discrete components (labeled C), such as pull-up resistors or coupling capacitors, which will not have any associated testability features. The PCA is tested, both in production
42、 (to verify correct manufacture) and in field service (to detect and locate faults), using automatic test equipment (ATE) to supply test signals to, and to collect test responses from, some or all of the component pins. The aim of the test structures described in this standard is to provide test acc
43、ess to individual component pins from the edge-connector to reduce or eliminate the need for the ATE to make direct physical contact via mechanical probes. The extent to which this aim can be satisfied will depend on the make-up of the PCA: The pins of components that conform either to this standard
44、 or to IEEE Std 1149.1-2001 will be accessible from the edge-connector, providing at least partial access to the pins of some non-conformant components. If this access is inadequate for testing purposes, additional probe access would need to be employed. 1Information on references can be found in Cl
45、ause 2. IEEE Std 1149.4-2010 IEEE Standard for a Mixed-Signal Test Bus 3 Copyright 2011 IEEE. All rights reserved. 1.3 Scope This standard defines a mixed-signal test bus architecture that provides the means of control and access to both analog and digital test signals such that the testability stru
46、cture for digital circuits described in IEEE Std 1149.1-2001 has been extended effectively to provide similar facilities for mixed-signal circuits. In addition to testing of interconnections in the conventional sense of IEEE Std 1149.1-2001, the mixed-signal test bus defined by this standard also pr
47、ovides the means for parametric testing and, optionally, the means to access internal test structures. The standard does not mandate implementation details of the test circuitry, although examples of conformant implementations are given for illustration. Further, the standard develops extensions to
48、Boundary-Scan Description Language (BSDL) as a means of describing key aspects of the implementation of this standard within a particular component. At present, the extensions to BSDL defined by this standard specifically omit the description of any and all analog parameters defined by the standard.
49、 1.3.1 Aims This standard defines test features to be included in a mixed-signal (analog and digital) component, together with associated test protocols, to provide standardized approaches to Interconnect test: Testing for opens and shorts among the interconnections in a PCA; Parametric test: Making analog characterization measurements and testing for presence and value of discrete components in a PCA; and Internal test: Testing the internal circuitry of the mixed-signal component itself regardless of whether it is part of a PCA. The standard does not
